moving more over to openpower-isa repo
rather invasive reduction of SPR regfile size done by dynamically creating an alternative SPR Enum
add sv_out2 to PowerDecode and PowerDecoder2 used for 2nd write (currently LD/ST update only)
add SVP64 dststep incrementing in PowerDecoder2, Testissuer and ISACaller
link up SVP64 RM Mode decoding into PowerDecoder2
add in SVP64 RM Mode decoder
add more sophisticated checking of whether SVP64 loop should continue PowerDecoder2
add detection of whether *full* 7-bit of RA is zero/non-zero this because RA_OR_ZERO in PowerDecoder2 needs to test if the full SVP64-extended register is zero
actually make it possible to disable svp64 on commandline of test_issuer.py
add option to cut out SVP64 from PowerDecoder2
whoops microwatt already allocates SPR 720
operating correctly, not directing MMU SPRs to SPR Pipeline, failure with PC likely due to ISACaller not supporting SPR 720
Revert "fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2" This reverts commit 0b31706069567c4124ebac487f238342cc540d79.
move SVP64 Extra decoders to separate module
fix syntax error
move SVP64PrefixDecoder to separate module
add PowerDecoder.no_in_vec
fix Bug 607 - unnecessary code added related to MMU in PowerDecoder2
fix Bug 603 - use SPR names/numbers from sprs.csv
add comments explaining split https://bugs.libre-soc.org/show_bug.cgi?id=606