correct migration of openpower-isa
more openpower import conversion
move over to from openpower imports
Add CR predication test case for TestIssuer Directly derived from the corresponding case in test_caller_svp64_predication.py It is expected to fail, until CR predication is implemented on TestIssuer.
Add 1<<r3 test cases to TestIssuer They fail, since it's not implemented yet.
Add a HDL test case, where we start at the middle of the VL loop It is expected to fail, since the HDL is not reentrant at this moment.
Fix typo
Add test case with all mask bits equal to zero
Add a test case for integer single predication
Enable remaining disabled test cases They all work, now, after the ISA Caller fixes.
Enable VCOMPRESS test case VEXPAND seems to have some issue in the Simulator maybe.
Add new twin predication case Equivalent to VCOMPRESS followed by VEXPAND.
Adjust twin predication cases for the new syntax
Add test cases for integer VCOMPRESS and VEXPAND In these cases, either srcmask or destmask is "always", so the corresponding mask should be all ones, instead of being fetched from the register file.
adjust syntax of SVP64 predicate test cas
naah. back to "sv." syntax for SVP64 assembly
Add predication test case, initially disabled Directly derived from a test in test_caller_svp64_predication.py The goal is to incrementally develop the TestIssuer FSMs, until it passes.
remove "sv." and replace with "sv" in all SVP64Asm
Bring a few test cases from test_caller_64.py 1) Test early out when destination is not a vector 2) Do not increment source register number for scalar operand
Test case for two successive SV instructions This checks that SRCSTEP is reset properly between instructions.