import from openpower.endian
move over to from openpower imports
sorting out shift_rot to use new output stage data structures shift_rot does not modify OV/32 so needs its own output stage similar to logical, SO is never set but is "read"
convert shift_rot test to new base accumulator style
format code
get shiftrot compunit working
adding mtspr tests
big reorg on PowerDecoder2, actually Decode2Execute1Type plan is to move the decoding of instruction fields closer to the CompUnits
no global variables in test suites
convert shift_rot tests to use common get_cu_inputs function
reorganise ALU tests, move get_cu_inputs function to common location
rename regspecs to give a consistent naming scheme the Decode phase needs to be able to associate regspec information with actual signals, back in Decode2Execute1Type. the simplest way to do this is to make the regspec register names consistent and actually refer *to* Decode2Execute1Type signals
remove xer so/ov, swap rs/rb to correct(?) order in shiftrot test
add first version of ShiftRot CompUnit test