convert from public static functions/properties for regspecs to member functions to obtain regspecs this allows pspec (containing XLEN) to be passed to the regspecs, which in turn allows them to be dynamically set by issuer_verilog.py and unit tests
add LDSTException output to MMU
rename IntegerData to FUBaseData
do not need FAST regs in MMU
add OP_DCBZ to mmu fsm, needs RA to be added to MMU pipe_data
mmu uses RB, go with it
add mmu initial pipe_data.py