add linux-5.7 unit test which showed a silly error: LDST requests through PortInterface were truncated to 48 bits, where linux uses the top 2 bits of an address for VM/guest (Quadrant 0-3)
add parent_pspec everywhere
format code
hack to fix UnusedElaboratables in src/soc/fu/mmu/test/test_pipe_caller.py
another batch of ready/valid i/o prefix-suffix swaps
replace data_o with o_data and data_i with i_data as well a little more care involved here due to names such as st_data_o and others
debug and stop on mmu test_pipe_caller.py
add a TestSRAM variant of LoadStore1, for being able to run unit MMU unit tests
set up LoadStore1 in ConfigMemoryPortInterface and hook it up in MMU
move MMU Testcase to openpower.test
import from openpower.endian
use openpower.test.common
more openpower-isa conversion
move over to from openpower imports
set initial_sprs, cleanup mfspr testprog
mfspr is RT, SPR
first testcase for mmu: case_mfspr_after_invalid_load
testcase for dcbz
dcbz and tlbie first test, still incomplete
fu/mmu/test/test_pipe_caller.py test case for mfspr