convert from public static functions/properties for regspecs to member functions to obtain regspecs this allows pspec (containing XLEN) to be passed to the regspecs, which in turn allows them to be dynamically set by issuer_verilog.py and unit tests
add CommonPipeSpec.__getattr__ to forward attributes from parent_pspec replaces CommonPipeSpec.draft_bitmanip
add parent_pspec everywhere
add comment about draft instructions
account for Mock absurdities
make bitmanip operations conditional on pspec.draft_bitmanip
format code
remove exception from data on FUBaseData, explicitly eq() it
add option to add exception type to FUBaseData (pipe_data)
rename IntegerData to FUBaseData
move over to from openpower imports
going on a bit of a "naming" spree, this for Jean-Paul to be able to identify operand records on pipelines
update README for pipe_data.py
comments on what goes into CommonPipeSpec
comments on IntegerData class
import PipeContext not FPPipeContext
remove xer_ca from DIV pipeline (took a bit of messing about)
whoops forgot that the mul pipeline is actually a pipeline (3 stage, first one)
noticed the regular pattern in all pipe_data.py (regspecs). removed manual Input/Output Data, use regspecs to create it, in IntegerData
move common functionality between PipeSpecs to soc.fu.pipe_data