convert shift_rot pipeline to XLEN=32/64
convert from public static functions/properties for regspecs to member functions to obtain regspecs this allows pspec (containing XLEN) to be passed to the regspecs, which in turn allows them to be dynamically set by issuer_verilog.py and unit tests
rename IntegerData to FUBaseData
sorting out shift_rot to use new output stage data structures shift_rot does not modify OV/32 so needs its own output stage similar to logical, SO is never set but is "read"
although shift-rot does not alter XER.so it still needs it as input for CR0
bug in andc and orc, complement was taking place on RA not RB
remove unneeded imports
noticed the regular pattern in all pipe_data.py (regspecs). removed manual Input/Output Data, use regspecs to create it, in IntegerData
remove rdflags in pipe_data.py (redundant)
rename regspecs to give a consistent naming scheme the Decode phase needs to be able to associate regspec information with actual signals, back in Decode2Execute1Type. the simplest way to do this is to make the regspec register names consistent and actually refer *to* Decode2Execute1Type signals
okaaay add a "rdflags" function which obtains the yes/no flags for each register to the CompUnit this to be used by the Decode phase
add shift-rot input record and use it
put RB in 2nd position (matching immediate) in ShiftRot Input Data
shiftrot uses LogicalOutputData not ALUOutputData
remove sticky overflow from Shift Rot pipeline
create common input pipe spec to avoid code-duplication
move common functionality between PipeSpecs to soc.fu.pipe_data
move FU IntegerData to directory below
create and use ShiftRotPipeSpec
add register specs to pipeline in/out so that they can be used to connect up Function Units to regfiles