clear out DEC in core.cur_state.dec due to spurious interrupt. this is slightly complicated. the STATE regfile contains pc, msr, svstate, dec, and tb, being a reflection of CoreState. reading from STATE regfile is on a one-clock delay. the DEC/TB FSM needs to decrement DEC and increment TB, by reading from the STATE regfile and then writing a new value. of course, the SPR pipeline has to get a word in edgeways as well. but... the complication comes in that it is the PowerDecoder2 which receives a *cached* copy of DEC, and this cached copy is what has (up until now) been out-of-date with what is in the STATE regfile. the hack-job-solution is to zero-out the cached copy when the SPR pipeline writes a new value to DEC. the DEC/TB FSM will then rewrite a correct value into it. given that PowerDecoder2 only uses the MSB of DEC (and the EE bit of MSR) to determine whether to fire an interrupt, this should be perfectly fine.
convert from public static functions/properties for regspecs to member functions to obtain regspecs this allows pspec (containing XLEN) to be passed to the regspecs, which in turn allows them to be dynamically set by issuer_verilog.py and unit tests
move DEC and TB into StateRegs, to make room in FastRegs also has the advantage that DEC and TB could generate an accurate interrupt
rename IntegerData to FUBaseData
move DEC and TB from StateRegs to FastRegs for several reasons first: SPR pipeline already has fast1 read/write second: a new DecodeStateIn/Out object would be needed instead just add FastRegs.DEC/TB to DecodeA/Out third: there is probably a third somewhere
add DEC/TB SPRs to spr pipeline
reduce regfile ports by creating separate STATE regfile
update docstrings
add spr test, add decode of spr in/out
add spr main stage
remove unneeded imports
noticed the regular pattern in all pipe_data.py (regspecs). removed manual Input/Output Data, use regspecs to create it, in IntegerData
convenience rename for spr pipe_data.py, consistent naming for PowerDecode2
add comments for SPR pipe_data
add SPR pipe_data.py