remove old code
move back to 3.3v on X3 VERSA ECP5 connector
swap jtag pinorder to match ulx3s
change LVCMOS level on versa ecp5 jtag to 2.5v
versa_ecp5.py add 4 arbitrarily assigned gpio pins to be used by Libre-SOC JTAG interface on ulx3s
add JTAG extension to versa_ecp5 then we can use it
add commented-out connection to JTAG in ECP5 litex
syntax error
disable gpio in litex core
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5|ulx3s85f] default of versa_ecp5, to build for different fpga targets, fix whitespace, delete ulx3s85f.py as it's no longer needed
record commands for building ECP5
florent/versa_ecp5.py remove uneccessary imports, specify actual import instead of evil 'import *'
add versa ecp5 fpga litex build script