big rename, global/search/replace of ready_o with o_ready and the other > 4 signals as well, valid_i -> i_valid > https://libera.irclog.whitequark.org/nmigen/2021-08-24#30728292; > to be consistent with nmigen standards
add detection and disable of LoadStore Wishbone based on JTAG command
get litex sim enabled with 32-bit wishbone bus
ld/st bus reduction test operational
first test of down-converted load/store from 64 to 32 bit
add in WishboneDownConvert into LoadStoreUnitInterface
clear sel on loadstore
format code
likewise cut across latest Minerva loadstore with line-for-line manual compare
port minerva cache fixes commit 3a0158919144757a2b369c9b750c72339e912f1d Author: Jean-François Nguyen <jf@lambdaconcept.com> Date: Wed Sep 11 01:34:46 2019 +0200 fetch,loadstore: Fix `{f,m}_busy` signal in case of a cache miss.
forward-port minerva loadstore bugfix commit a03a72e04764dc976d85ea44b1cf0767e240b81f Author: Jean-François Nguyen <jf@lambdaconcept.com> Date: Thu Apr 30 12:23:36 2020 +0200 loadstore: fix conflict between write buffer and dcache refill.
add bare wishbone option to TestIssuer, sort out ports
minor reorg on how Bus and Config classes are set up
need args to WishboneArbiter, match data width size
clean up output from BareLoadStoreUnit
code-morph which redirects lsmem unit test through new ConfigLoadStoreUnit this to allow wishbone-SRAM test version to be tested with the same unit test
dynamically specify wishbone layout (no longer hardcoded addr/data)
extra parameterification of minerva LoadStoreUnits
rename LoadStoreInterface signals to include _i and _o suffixes got fed up of not knowing which Signal was which direction
whitespace