add a new make target for setting coldboot firmware at 0xfff0_0000 put reset values of pc and msr into Issuer explicitly on reset
add alternative pc_reset argument to issuer_verilog.py which propagates right the way down to core.py next to msr_reset it is now possible to set the pc_reset value. these actually have to go into the regfile as initial values, which will be fun for an ASIC
sigh, monitor DEC/TB StateRegs "properly" so that the Issuer DEC/TB FSM does not end up in a race condition with the SPR pipeline for writing to DEC or TB
whoops MFSPR DEC/TB was reading from FastRegs not StateRegs also TBU
comments
move DEC and TB into StateRegs, to make room in FastRegs also has the advantage that DEC and TB could generate an accurate interrupt
add pause_dec_tb signal (not very sophisticated) to Core TODO, detect MTSPR and DEC/TB SPR being written to, but for now just detect an entire SPR pipeline
add linux-5.7 unit test which showed a silly error: LDST requests through PortInterface were truncated to 48 bits, where linux uses the top 2 bits of an address for VM/guest (Quadrant 0-3)
allow MSR reset to default to a value set by issuer_verilog.py
starting to hack in fetch failed (including OP_FETCH_FAILED) going really badly as far as code-readability and clean design is concerned but is progressing a truly dreadful hack: OP_TRAP works (LDST Exceptions) because the main decoder (PowerDecoder2) is used by core for the Trap pipeline. unnnnfortunately... for MMU, a *Satellite* decoder (PowerDecodeSubset) is used. and Satellite decoders *only* understand *instructions*. (which they part-decode locally). therefore a manual override of the satellite decoder insn_type and fn_unit is required when OP_FETCH_FAILED occurs. truly awful.
in a terrible botched way, get at I-Cache and set it up this is for adding in I-Cache and MMU into core.
connect up I-Cache to FetchUnitInterface FetchUnitInterface may in turn need redesigning, but that is another story
make icache accessible to core, working back to TestIssuer
add a bitvector remap function, the plan is to use it to reduce the size of regfile bitvector hazards
use new namedtuple in core when calling regspec_decode()
add module parameter to regspec_decode and therefore to get_byregfiles as well
better name for read latch in core.py
remove redundant / mis-named variable in core
code-comments
remove unneeded data structure in core