Add lfsr with 11 bits
[soc.git] / TLB / src / LFSR.py
1 from nmigen import Module, Signal
2 from nmigen.cli import main
3
4 size = 11
5
6 class LFSR:
7 def __init__(self):
8
9 # Output
10 self.enable = Signal(1)
11 self.o = Signal(size)
12
13 def elaborate(self, platform=None):
14 m = Module()
15
16 for i in range(size):
17 with m.If(self.enable):
18 if i == 0:
19 zero = self.o[0]
20 one = self.o[1]
21 m.d.sync += self.o[0].eq(zero ^ one)
22 if i == 3:
23 zero = self.o[0]
24 three = self.o[4]
25 m.d.sync += self.o[3].eq(zero ^ three)
26 else:
27 prev = self.o[(i + 1) % size]
28 m.d.sync += self.o[i].eq(prev)
29 return m
30