rename LFSR -> LFSR2
[soc.git] / TLB / test / test_LFSR2.py
1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
3 from ..src.LFSR2 import LFSR, LFSRPolynomial, LFSR_POLY_3
4 from nmigen.back.pysim import Simulator, Delay, Tick
5 import unittest
6
7
8 class TestLFSR(unittest.TestCase):
9 def test_poly(self):
10 v = LFSRPolynomial()
11 self.assertEqual(repr(v), "LFSRPolynomial([0])")
12 self.assertEqual(str(v), "1")
13 v = LFSRPolynomial([1])
14 self.assertEqual(repr(v), "LFSRPolynomial([1, 0])")
15 self.assertEqual(str(v), "x + 1")
16 v = LFSRPolynomial([0, 1])
17 self.assertEqual(repr(v), "LFSRPolynomial([1, 0])")
18 self.assertEqual(str(v), "x + 1")
19 v = LFSRPolynomial([1, 2])
20 self.assertEqual(repr(v), "LFSRPolynomial([2, 1, 0])")
21 self.assertEqual(str(v), "x^2 + x + 1")
22 v = LFSRPolynomial([2])
23 self.assertEqual(repr(v), "LFSRPolynomial([2, 0])")
24 self.assertEqual(str(v), "x^2 + 1")
25 self.assertEqual(str(LFSR_POLY_3), "x^3 + x^2 + 1")
26
27 def test_lfsr_3(self):
28 module = LFSR(LFSR_POLY_3)
29 traces = [module.state, module.enable]
30 with Simulator(module,
31 vcd_file=open("Waveforms/test_LFSR2.vcd", "w"),
32 gtkw_file=open("Waveforms/test_LFSR2.gtkw", "w"),
33 traces=traces) as sim:
34 sim.add_clock(1e-6, 0.25e-6)
35 delay = Delay(1e-7)
36
37 def async_process():
38 yield module.enable.eq(0)
39 yield Tick()
40 self.assertEqual((yield module.state), 0x1)
41 yield Tick()
42 self.assertEqual((yield module.state), 0x1)
43 yield module.enable.eq(1)
44 yield Tick()
45 yield delay
46 self.assertEqual((yield module.state), 0x2)
47 yield Tick()
48 yield delay
49 self.assertEqual((yield module.state), 0x5)
50 yield Tick()
51 yield delay
52 self.assertEqual((yield module.state), 0x3)
53 yield Tick()
54 yield delay
55 self.assertEqual((yield module.state), 0x7)
56 yield Tick()
57 yield delay
58 self.assertEqual((yield module.state), 0x6)
59 yield Tick()
60 yield delay
61 self.assertEqual((yield module.state), 0x4)
62 yield Tick()
63 yield delay
64 self.assertEqual((yield module.state), 0x1)
65 yield Tick()
66
67 sim.add_process(async_process)
68 sim.run()