src/scoreboard/group_picker.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Cat, Elaboratable
   4
   5
   6 class PriorityPicker(Elaboratable):
   7     """ implements a priority-picker.  input: N bits, output: N bits
   8     """
   9     def __init__(self, wid):
  10         self.wid = wid
  11         # inputs
  12         self.i = Signal(wid, reset_less=True)
  13         self.o = Signal(wid, reset_less=True)
  14
  15     def elaborate(self, platform):
  16         m = Module()
  17
  18         res = []
  19         for i in range(0, self.wid):
  20             tmp = Signal(reset_less = True)
  21             if i == 0:
  22                 m.d.comb += tmp.eq(self.i[0])
  23             else:
  24                 m.d.comb += tmp.eq((~tmp) & self.i[i])
  25             res.append(tmp)
  26
  27         # we like Cat(*xxx).  turn lists into concatenated bits
  28         m.d.comb += self.o.eq(Cat(*res))
  29
  30         return m
  31
  32     def __iter__(self):
  33         yield self.i
  34         yield self.o
  35
  36     def ports(self):
  37         return list(self)
  38
  39
  40 class GroupPicker(Elaboratable):
  41     """ implements 10.5 mitch alsup group picker, p27
  42     """
  43     def __init__(self, wid):
  44         self.gp_wid = wid
  45         # inputs
  46         self.readable_i = Signal(wid, reset_less=True) # readable in (top)
  47         self.writable_i = Signal(wid, reset_less=True) # writable in (top)
  48         self.rel_req_i = Signal(wid, reset_less=True) # release request in (top)
  49
  50         # outputs
  51         self.go_rd_o = Signal(wid, reset_less=True)  # go read (bottom)
  52         self.go_wr_o = Signal(wid, reset_less=True)  # go write (bottom)
  53
  54     def elaborate(self, platform):
  55         m = Module()
  56
  57         m.submodules.rpick = rpick = PriorityPicker(self.gp_wid)
  58         m.submodules.wpick = wpick = PriorityPicker(self.gp_wid)
  59
  60         # combine release (output ready signal) with writeable
  61         m.d.comb += wpick.i.eq(self.writable_i & self.rel_req_i)
  62         m.d.comb += self.go_wr_o.eq(wpick.o)
  63
  64         m.d.comb += rpick.i.eq(self.readable_i)
  65         m.d.comb += self.go_rd_o.eq(rpick.o)
  66
  67         return m
  68
  69     def __iter__(self):
  70         yield self.readable_i
  71         yield self.writable_i
  72         yield self.rel_req_i
  73         yield self.go_rd_o
  74         yield self.go_wr_o
  75
  76     def ports(self):
  77         return list(self)
  78
  79
  80 def grp_pick_sim(dut):
  81     yield dut.dest_i.eq(1)
  82     yield dut.issue_i.eq(1)
  83     yield
  84     yield dut.issue_i.eq(0)
  85     yield
  86     yield dut.src1_i.eq(1)
  87     yield dut.issue_i.eq(1)
  88     yield
  89     yield
  90     yield
  91     yield dut.issue_i.eq(0)
  92     yield
  93     yield dut.go_read_i.eq(1)
  94     yield
  95     yield dut.go_read_i.eq(0)
  96     yield
  97     yield dut.go_write_i.eq(1)
  98     yield
  99     yield dut.go_write_i.eq(0)
 100     yield
 101
 102 def test_grp_pick():
 103     dut = GroupPicker(4)
 104     vl = rtlil.convert(dut, ports=dut.ports())
 105     with open("test_grp_pick.il", "w") as f:
 106         f.write(vl)
 107
 108     run_simulation(dut, grp_pick_sim(dut), vcd_name='test_grp_pick.vcd')
 109
 110 if __name__ == '__main__':
 111     test_grp_pick()