src/scoreboard/ldst_matrix.py

   1 """ Mitch Alsup 6600-style LD/ST Memory Scoreboard Matrix (sparse vector)
   2
   3 6600 LD/ST Dependency Table Matrix inputs / outputs
   4 ---------------------------------------------------
   5
   6 Relevant comments (p45-46):
   7
   8 * If there are no WAR dependencies on a Load instruction with a computed
   9   address it can assert Bank_Addressable and Translate_Addressable.
  10
  11 * If there are no RAW dependencies on a Store instruction with both a
  12   write permission and store data present it can assert Bank_Addressable
  13
  14 Relevant bugreports:
  15 * http://bugs.libre-riscv.org/show_bug.cgi?id=81
  16
  17 """
  18
  19 from nmigen.compat.sim import run_simulation
  20 from nmigen.cli import verilog, rtlil
  21 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
  22
  23 from ldst_dep_cell import LDSTDepCell
  24
  25
  26 class LDSTDepMatrix(Elaboratable):
  27     """ implements 11.4.12 mitch alsup LD/ST Dependency Matrix, p46
  28         actually a sparse matrix along the diagonal.
  29
  30         load-hold-store and store-hold-load accumulate in a priority-picking
  31         fashion, ORing together.  the OR gate from the dependency cell is
  32         here.
  33     """
  34     def __init__(self, n_ldst):
  35         self.n_ldst = n_ldst                  # X and Y (FUs)
  36         self.load_i = Signal(n_ldst, reset_less=True)  # load pending in
  37         self.stor_i = Signal(n_ldst, reset_less=True)  # store pending in
  38         self.issue_i = Signal(n_ldst, reset_less=True) # Issue in
  39
  40         self.load_hit_i = Signal(n_ldst, reset_less=True) # load hit in
  41         self.stwd_hit_i = Signal(n_ldst, reset_less=True) # store w/data hit in
  42
  43         # outputs
  44         self.ld_hold_st_o = Signal(reset_less=True) # load holds st out
  45         self.st_hold_ld_o = Signal(reset_less=True) # st holds load out
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49
  50         # ---
  51         # matrix of dependency cells
  52         # ---
  53         dm = Array(LDSTDepCell() for f in range(self.n_ldst))
  54         for fu in range(self.n_ldst):
  55             setattr(m.submodules, "dm_fu%d" % (fu), dm[fu])
  56
  57         # ---
  58         # connect Function Unit vector
  59         # ---
  60         lhs_l = []
  61         shl_l = []
  62         load_l = []
  63         stor_l = []
  64         issue_l = []
  65         lh_l = []
  66         sh_l = []
  67         for fu in range(self.n_ldst):
  68             dc = dm[fu]
  69             # accumulate load-hold-store / store-hold-load bits
  70             lhs_l.append(dc.ld_hold_st_o)
  71             shl_l.append(dc.st_hold_ld_o)
  72             # accumulate inputs (for Cat'ing later) - TODO: must be a better way
  73             load_l.append(dc.load_i)
  74             stor_l.append(dc.stor_i)
  75             issue_l.append(dc.issue_i)
  76             lh_l.append(dc.load_hit_i)
  77             sh_l.append(dc.stwd_hit_i)
  78
  79         # connect cell inputs using Cat(*list_of_stuff)
  80         m.d.comb += [Cat(*load_l).eq(self.load_i),
  81                      Cat(*stor_l).eq(self.stor_i),
  82                      Cat(*issue_l).eq(self.issue_i),
  83                      Cat(*lh_l).eq(self.load_hit_i),
  84                      Cat(*sh_l).eq(self.stwd_hit_i),
  85                     ]
  86         # set the load-hold-store / store-hold-load OR-accumulated outputs
  87         m.d.comb += self.ld_hold_st_o.eq(Cat(*lhs_l).bool())
  88         m.d.comb += self.st_hold_ld_o.eq(Cat(*shl_l).bool())
  89
  90         return m
  91
  92     def __iter__(self):
  93         yield self.load_i
  94         yield self.stor_i
  95         yield self.issue_i
  96         yield self.load_hit_i
  97         yield self.stwd_hit_i
  98         yield self.ld_hold_st_o
  99         yield self.st_hold_ld_o
 100
 101     def ports(self):
 102         return list(self)
 103
 104 def d_matrix_sim(dut):
 105     """ XXX TODO
 106     """
 107     yield dut.dest_i.eq(1)
 108     yield dut.issue_i.eq(1)
 109     yield
 110     yield dut.issue_i.eq(0)
 111     yield
 112     yield dut.src1_i.eq(1)
 113     yield dut.issue_i.eq(1)
 114     yield
 115     yield dut.issue_i.eq(0)
 116     yield
 117     yield dut.go_rd_i.eq(1)
 118     yield
 119     yield dut.go_rd_i.eq(0)
 120     yield
 121     yield dut.go_wr_i.eq(1)
 122     yield
 123     yield dut.go_wr_i.eq(0)
 124     yield
 125
 126 def test_d_matrix():
 127     dut = LDSTDepMatrix(n_ldst=4)
 128     vl = rtlil.convert(dut, ports=dut.ports())
 129     with open("test_ld_st_matrix.il", "w") as f:
 130         f.write(vl)
 131
 132     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_ld_st_matrix.vcd')
 133
 134 if __name__ == '__main__':
 135     test_d_matrix()