src/soc/TLB/test/test_cam_entry.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from TestUtil.test_helper import assert_eq, assert_ne, assert_op
   4 from TLB.CamEntry import CamEntry
   5
   6 # This function allows for the easy setting of values to the Cam Entry
   7 # Arguments:
   8 #   dut: The CamEntry being tested
   9 #   c (command): NA (0), Read (1), Write (2), Reserve (3)
  10 #   d (data): The data to be set
  11 def set_cam_entry(dut, c, d):
  12     # Write desired values
  13     yield dut.command.eq(c)
  14     yield dut.data_in.eq(d)
  15     yield
  16     # Reset all lines
  17     yield dut.command.eq(0)
  18     yield dut.data_in.eq(0)
  19     yield
  20
  21 # Checks the data state of the CAM entry
  22 # Arguments:
  23 #   dut: The CamEntry being tested
  24 #   d (Data): The expected data
  25 #   op (Operation): (0 => ==), (1 => !=)
  26 def check_data(dut, d, op):
  27     out_d = yield dut.data
  28     assert_op("Data", out_d, d, op)
  29
  30 # Checks the match state of the CAM entry
  31 # Arguments:
  32 #   dut: The CamEntry being tested
  33 #   m (Match): The expected match
  34 #   op (Operation): (0 => ==), (1 => !=)
  35 def check_match(dut, m, op):
  36     out_m = yield dut.match
  37     assert_op("Match", out_m, m, op)
  38
  39 # Checks the state of the CAM entry
  40 # Arguments:
  41 #   dut: The CamEntry being tested
  42 #   d (data): The expected data
  43 #   m (match): The expected match
  44 #   d_op (Operation): Operation for the data assertion (0 => ==), (1 => !=)
  45 #   m_op (Operation): Operation for the match assertion (0 => ==), (1 => !=)
  46 def check_all(dut, d, m, d_op, m_op):
  47     yield from check_data(dut, d, d_op)
  48     yield from check_match(dut, m, m_op)
  49
  50 # This tbench goes through the paces of testing the CamEntry module
  51 # It is done by writing and then reading various combinations of key/data pairs
  52 # and reading the results with varying keys to verify the resulting stored
  53 # data is correct.
  54 def tbench(dut):
  55     # Check write
  56     command = 2
  57     data = 1
  58     match = 0
  59     yield from set_cam_entry(dut, command, data)
  60     yield from check_all(dut, data, match, 0, 0)
  61
  62     # Check read miss
  63     command = 1
  64     data = 2
  65     match = 0
  66     yield from set_cam_entry(dut, command, data)
  67     yield from check_all(dut, data, match, 1, 0)
  68
  69     # Check read hit
  70     command = 1
  71     data = 1
  72     match = 1
  73     yield from set_cam_entry(dut, command, data)
  74     yield from check_all(dut, data, match, 0, 0)
  75
  76     # Check overwrite
  77     command = 2
  78     data = 5
  79     match = 0
  80     yield from set_cam_entry(dut, command, data)
  81     yield
  82     yield from check_all(dut, data, match, 0, 0)
  83
  84     # Check read hit
  85     command = 1
  86     data = 5
  87     match = 1
  88     yield from set_cam_entry(dut, command, data)
  89     yield from check_all(dut, data, match, 0, 0)
  90
  91     # Check reset
  92     command = 3
  93     data = 0
  94     match = 0
  95     yield from set_cam_entry(dut, command, data)
  96     yield from check_all(dut, data, match, 0, 0)
  97
  98     # Extra clock cycle for waveform
  99     yield
 100
 101
 102 def test_camentry():
 103     dut = CamEntry(4)
 104     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_cam_entry.vcd")
 105     print("CamEntry Unit Test Success")
 106
 107
 108 if __name__ == "__main__":
 109     test_camentry()
 110