1 """demonstration of nmigen-soc SRAM behind a wishbone bus
3 * https://bugs.libre-soc.org/show_bug.cgi?id=382
5 from nmigen_soc
.wishbone
.sram
import SRAM
6 from nmigen
import Memory
, Signal
, Module
8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
10 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
12 memory
= Memory(width
=64, depth
=16)
13 sram
= SRAM(memory
=memory
, granularity
=16)
15 # valid wishbone signals include
27 m
.submodules
.sram
= sram
31 def print_sig(sig
, format
=None):
33 print(f
"{sig.__repr__()} = {(yield sig)}")
35 print(f
"{sig.__repr__()} = {hex((yield sig))}")
38 # enable necessary signals for write
40 yield sram
.bus
.sel
[en
].eq(1)
41 yield sram
.bus
.we
.eq(1)
42 yield sram
.bus
.cyc
.eq(1)
43 yield sram
.bus
.stb
.eq(1)
45 # put data and address on bus
46 yield sram
.bus
.adr
.eq(0x4)
47 yield sram
.bus
.dat_w
.eq(0xdeadbeef)
50 # set necessary signal to read bus
52 yield sram
.bus
.we
.eq(0)
53 yield sram
.bus
.adr
.eq(0)
54 yield sram
.bus
.cyc
.eq(1)
55 yield sram
.bus
.stb
.eq(1)
58 # see sync_behaviors.py
59 # for why we need Settle()
60 # debug print the bus address/data
62 yield from print_sig(sram
.bus
.adr
)
63 yield from print_sig(sram
.bus
.dat_r
, "h")
66 data
= yield sram
.bus
.dat_r
69 # set necessary signal to read bus
71 yield sram
.bus
.we
.eq(0)
72 yield sram
.bus
.adr
.eq(0x4)
73 yield sram
.bus
.cyc
.eq(1)
74 yield sram
.bus
.stb
.eq(1)
77 # see sync_behaviors.py
78 # for why we need Settle()
79 # debug print the bus address/data
81 yield from print_sig(sram
.bus
.adr
)
82 yield from print_sig(sram
.bus
.dat_r
, "h")
85 data
= yield sram
.bus
.dat_r
86 assert data
== 0xdeadbeef
89 yield sram
.bus
.cyc
.eq(0)
90 yield sram
.bus
.stb
.eq(0)
93 sim_writer
= sim
.write_vcd(f
"{__file__[:-3]}.vcd")
96 sim
.add_sync_process(process
)