src/soc/clock/dummypll.py

   1 """a Dummy PLL module to be replaced by a real one
   2 """
   3
   4 from nmigen import (Module, Signal, Elaboratable, Const)
   5 from nmigen.cli import rtlil
   6
   7 class DummyPLL(Elaboratable):
   8     def __init__(self):
   9         self.clk_24_i = Signal(reset_less=True) # 24 mhz external incoming
  10         self.clk_sel_i = Signal(2, reset_less=True) # PLL selection
  11         self.clk_pll_o = Signal(reset_less=True)  # output fake PLL clock
  12         self.pll_18_o = Signal(reset_less=True)  # 16-divide from PLL
  13         self.clk_lck_o = Signal(reset_less=True)  # output fake PLL "lock"
  14
  15     def elaborate(self, platform):
  16         m = Module()
  17         m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
  18         # just get something, stops yosys destroying (optimising) these out
  19         m.d.comb += self.pll_18_o.eq(self.clk_24_i)
  20         with m.If(self.clk_sel_i == Const(0, 2)):
  21             m.d.comb += self.clk_lck_o.eq(self.clk_24_i)
  22
  23         return m
  24
  25     def ports(self):
  26         return [self.clk_24_i, self.clk_sel_i, self.clk_pll_o,
  27                 self.pll_18_o, self.clk_lck_o]
  28
  29
  30 if __name__ == '__main__':
  31     dut = ClockSelect()
  32
  33     vl = rtlil.convert(dut, ports=dut.ports())
  34     with open("test_dummy_pll.il", "w") as f:
  35         f.write(vl)
  36