e772eb8c6163871e09b801a4cbd9e55fa5dcab37
1 from soc
.minerva
.units
.fetch
import FetchUnitInterface
2 from nmigen
import Signal
, Module
, Elaboratable
, Mux
3 from nmigen
.utils
import log2_int
5 from nmigen
.back
.pysim
import Simulator
, Settle
6 from soc
.config
.ifetch
import ConfigFetchUnit
7 from collections
import namedtuple
8 from nmigen
.cli
import rtlil
10 from soc
.config
.test
.test_loadstore
import TestMemPspec
13 def read_from_addr(dut
, addr
):
14 yield dut
.a_pc_i
.eq(addr
)
15 yield dut
.a_valid_i
.eq(1)
16 yield dut
.a_stall_i
.eq(1)
18 yield dut
.a_stall_i
.eq(0)
21 while (yield dut
.f_busy_o
):
23 assert (yield dut
.a_valid_i
)
24 return (yield dut
.f_instr_o
)
27 def tst_lsmemtype(ifacetype
):
29 pspec
= TestMemPspec(ldst_ifacetype
=ifacetype
,
30 imem_ifacetype
=ifacetype
, addr_wid
=64,
33 dut
= ConfigFetchUnit(pspec
).fu
34 vl
= rtlil
.convert(dut
, ports
=[]) # TODOdut.ports())
35 with
open("test_fetch_%s.il" % ifacetype
, "w") as f
:
38 m
.submodules
.dut
= dut
47 values
= [random
.randint(0, (1<<32)-1) for x
in range(16)]
48 for addr
, val
in enumerate(values
):
49 yield mem
._array
[addr
].eq(val
)
51 for addr
, val
in enumerate(values
):
52 x
= yield from read_from_addr(dut
, addr
<< 2)
53 print ("addr, val", addr
, hex(val
), hex(x
))
56 sim
.add_sync_process(process
)
57 with sim
.write_vcd("test_fetch_%s.vcd" % ifacetype
, traces
=[]):
60 if __name__
== '__main__':
61 #tst_lsmemtype('test_bare_wb')
62 tst_lsmemtype('testmem')