src/soc/config/test/test_fetch.py

   1 from soc.minerva.units.fetch import FetchUnitInterface
   2 from nmigen import Signal, Module, Elaboratable, Mux
   3 from nmigen.utils import log2_int
   4 import random
   5 from nmigen.back.pysim import Simulator, Settle
   6 from soc.config.ifetch import ConfigFetchUnit
   7 from collections import namedtuple
   8 from nmigen.cli import rtlil
   9
  10 from soc.config.test.test_loadstore import TestMemPspec
  11
  12 import sys
  13 sys.setrecursionlimit(10**6)
  14
  15 def read_from_addr(dut, addr):
  16     yield dut.a_pc_i.eq(addr)
  17     yield dut.a_valid_i.eq(1)
  18     yield dut.f_valid_i.eq(1)
  19     yield dut.a_stall_i.eq(1)
  20     yield
  21     yield dut.a_stall_i.eq(0)
  22     yield
  23     yield Settle()
  24     while (yield dut.f_busy_o):
  25         yield
  26     res = (yield dut.f_instr_o)
  27
  28     yield dut.a_valid_i.eq(0)
  29     yield dut.f_valid_i.eq(0)
  30     yield
  31     return res
  32
  33
  34 def tst_lsmemtype(ifacetype, sram_depth=32):
  35     m = Module()
  36     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
  37                          imem_ifacetype=ifacetype, addr_wid=64,
  38                                                    mask_wid=4,
  39                                                    reg_wid=32,
  40                          imem_test_depth=sram_depth)
  41     dut = ConfigFetchUnit(pspec).fu
  42     vl = rtlil.convert(dut, ports=[]) # TODOdut.ports())
  43     with open("test_fetch_%s.il" % ifacetype, "w") as f:
  44         f.write(vl)
  45
  46     m.submodules.dut = dut
  47
  48     sim = Simulator(m)
  49     sim.add_clock(1e-6)
  50
  51     mem = dut._get_memory()
  52
  53     def process():
  54
  55         values = [random.randint(0, (1<<32)-1) for x in range(16)]
  56         for addr, val in enumerate(values):
  57             yield mem._array[addr].eq(val)
  58         yield Settle()
  59
  60         for addr, val in enumerate(values):
  61             x = yield from read_from_addr(dut, addr << 2)
  62             print ("addr, val", addr, hex(val), hex(x))
  63             assert x == val
  64
  65     sim.add_sync_process(process)
  66     with sim.write_vcd("test_fetch_%s.vcd" % ifacetype, traces=[]):
  67         sim.run()
  68
  69 if __name__ == '__main__':
  70     tst_lsmemtype('test_bare_wb', sram_depth=32768)
  71     tst_lsmemtype('testmem')