src/soc/config/test/test_loadstore.py

   1 from soc.minerva.units.loadstore import LoadStoreUnitInterface
   2 from nmigen import Signal, Module, Elaboratable, Mux
   3 from nmigen.utils import log2_int
   4 import random
   5 from nmigen.back.pysim import Simulator, Settle
   6 from soc.config.loadstore import ConfigLoadStoreUnit
   7 from collections import namedtuple
   8 from nmigen.cli import rtlil
   9 from unittest.mock import Mock
  10
  11 TestMemPspec = Mock  # might as well use Mock, it does the job
  12
  13
  14 def write_to_addr(dut, addr, value):
  15     yield dut.x_addr_i.eq(addr)
  16     yield dut.x_st_data_i.eq(value)
  17     yield dut.x_st_i.eq(1)
  18     yield dut.x_mask_i.eq(-1)
  19     yield dut.x_valid_i.eq(1)
  20     yield dut.x_stall_i.eq(1)
  21     yield dut.m_valid_i.eq(1)
  22     yield
  23     yield
  24
  25     yield dut.x_stall_i.eq(0)
  26     yield
  27     yield
  28     yield dut.x_st_i.eq(0)
  29     while (yield dut.x_busy_o):
  30         yield
  31
  32
  33 def read_from_addr(dut, addr):
  34     yield dut.x_addr_i.eq(addr)
  35     yield dut.x_ld_i.eq(1)
  36     yield dut.x_valid_i.eq(1)
  37     yield dut.x_stall_i.eq(1)
  38     yield
  39     yield dut.x_stall_i.eq(0)
  40     yield
  41     yield dut.x_ld_i.eq(0)
  42     yield Settle()
  43     while (yield dut.x_busy_o):
  44         yield
  45     assert (yield dut.x_valid_i)
  46     return (yield dut.m_ld_data_o)
  47
  48
  49 def write_byte(dut, addr, val):
  50     offset = addr & 0x3
  51     yield dut.x_addr_i.eq(addr)
  52     yield dut.x_st_data_i.eq(val << (offset * 8))
  53     yield dut.x_st_i.eq(1)
  54     yield dut.x_mask_i.eq(1 << offset)
  55     print("write_byte", addr, bin(1 << offset), hex(val << (offset*8)))
  56     yield dut.x_valid_i.eq(1)
  57     yield dut.m_valid_i.eq(1)
  58
  59     yield
  60     yield dut.x_st_i.eq(0)
  61     while (yield dut.x_busy_o):
  62         yield
  63
  64
  65 def read_byte(dut, addr):
  66     offset = addr & 0x3
  67     yield dut.x_addr_i.eq(addr)
  68     yield dut.x_ld_i.eq(1)
  69     yield dut.x_valid_i.eq(1)
  70     yield
  71     yield dut.x_ld_i.eq(0)
  72     yield Settle()
  73     while (yield dut.x_busy_o):
  74         yield
  75     assert (yield dut.x_valid_i)
  76     val = (yield dut.m_ld_data_o)
  77     print("read_byte", addr, offset, hex(val))
  78     return (val >> (offset * 8)) & 0xff
  79
  80
  81 def tst_lsmemtype(ifacetype):
  82     m = Module()
  83     pspec = TestMemPspec(ldst_ifacetype=ifacetype,
  84                          imem_ifacetype='', addr_wid=64,
  85                          mask_wid=4,
  86                          wb_data_wid=16,
  87                          reg_wid=32)
  88     dut = ConfigLoadStoreUnit(pspec).lsi
  89     vl = rtlil.convert(dut, ports=[])  # TODOdut.ports())
  90     with open("test_loadstore_%s.il" % ifacetype, "w") as f:
  91         f.write(vl)
  92
  93     m.submodules.dut = dut
  94
  95     sim = Simulator(m)
  96     sim.add_clock(1e-6)
  97
  98     def process():
  99
 100         values = [random.randint(0, 255) for x in range(0)]
 101         for addr, val in enumerate(values):
 102             yield from write_byte(dut, addr, val)
 103             x = yield from read_from_addr(dut, addr << 2)
 104             print("addr, val", addr, hex(val), hex(x))
 105             x = yield from read_byte(dut, addr)
 106             print("addr, val", addr, hex(val), hex(x))
 107             assert x == val
 108
 109         values = [random.randint(0, (1 << 32)-1) for x in range(16)]
 110
 111         for addr, val in enumerate(values):
 112             yield from write_to_addr(dut, addr << 2, val)
 113             x = yield from read_from_addr(dut, addr << 2)
 114             print("addr, val", addr, hex(val), hex(x))
 115             assert x == val
 116
 117     sim.add_sync_process(process)
 118     with sim.write_vcd("test_loadstore_%s.vcd" % ifacetype, traces=[]):
 119         sim.run()
 120
 121
 122 if __name__ == '__main__':
 123     tst_lsmemtype('test_bare_wb')
 124     tst_lsmemtype('testmem')