src/soc/config/test/test_loadstore.py

   1 from soc.minerva.units.loadstore import LoadStoreUnitInterface
   2 from nmigen import Signal, Module, Elaboratable, Mux
   3 from nmigen.utils import log2_int
   4 import random
   5 from nmigen.back.pysim import Simulator, Settle
   6 from soc.config.loadstore import ConfigLoadStoreUnit
   7 from collections import namedtuple
   8 from nmigen.cli import rtlil
   9
  10 TestMemPspec = namedtuple('TestMemPspec', ['ldst_ifacetype',
  11                              'addr_wid', 'mask_wid', 'reg_wid'])
  12
  13 def write_to_addr(dut, addr, value):
  14     yield dut.x_addr_i.eq(addr)
  15     yield dut.x_st_data_i.eq(value)
  16     yield dut.x_st_i.eq(1)
  17     yield dut.x_mask_i.eq(-1)
  18     yield dut.x_valid_i.eq(1)
  19     yield dut.x_stall_i.eq(1)
  20     yield dut.m_valid_i.eq(1)
  21     yield
  22     yield
  23
  24     yield dut.x_stall_i.eq(0)
  25     yield
  26     yield dut.x_st_i.eq(0)
  27     while (yield dut.x_busy_o):
  28         yield
  29
  30
  31 def read_from_addr(dut, addr):
  32     yield dut.x_addr_i.eq(addr)
  33     yield dut.x_ld_i.eq(1)
  34     yield dut.x_valid_i.eq(1)
  35     yield dut.x_stall_i.eq(1)
  36     yield
  37     yield dut.x_stall_i.eq(0)
  38     yield
  39     yield dut.x_ld_i.eq(0)
  40     yield Settle()
  41     while (yield dut.x_busy_o):
  42         yield
  43     assert (yield dut.x_valid_i)
  44     return (yield dut.m_ld_data_o)
  45
  46
  47 def write_byte(dut, addr, val):
  48     offset = addr & 0x3
  49     yield dut.x_addr_i.eq(addr)
  50     yield dut.x_st_data_i.eq(val << (offset * 8))
  51     yield dut.x_st_i.eq(1)
  52     yield dut.x_mask_i.eq(1 << offset)
  53     print ("write_byte", addr, bin(1<<offset), hex(val<<(offset*8)))
  54     yield dut.x_valid_i.eq(1)
  55     yield dut.m_valid_i.eq(1)
  56
  57     yield
  58     yield dut.x_st_i.eq(0)
  59     while (yield dut.x_busy_o):
  60         yield
  61
  62
  63 def read_byte(dut, addr):
  64     offset = addr & 0x3
  65     yield dut.x_addr_i.eq(addr)
  66     yield dut.x_ld_i.eq(1)
  67     yield dut.x_valid_i.eq(1)
  68     yield
  69     yield dut.x_ld_i.eq(0)
  70     yield Settle()
  71     while (yield dut.x_busy_o):
  72         yield
  73     assert (yield dut.x_valid_i)
  74     val = (yield dut.m_ld_data_o)
  75     print ("read_byte", addr, offset, hex(val))
  76     return (val >> (offset * 8)) & 0xff
  77
  78
  79 def tst_lsmemtype(ifacetype):
  80     m = Module()
  81     pspec = TestMemPspec(ldst_ifacetype=ifacetype, addr_wid=64,
  82                                                    mask_wid=4,
  83                                                    reg_wid=32)
  84     dut = ConfigLoadStoreUnit(pspec).lsi
  85     vl = rtlil.convert(dut, ports=[]) # TODOdut.ports())
  86     with open("test_loadstore_%s.il" % ifacetype, "w") as f:
  87         f.write(vl)
  88
  89     m.submodules.dut = dut
  90
  91     sim = Simulator(m)
  92     sim.add_clock(1e-6)
  93
  94     def process():
  95
  96         values = [random.randint(0, 255) for x in range(16*4)]
  97         for addr, val in enumerate(values):
  98             yield from write_byte(dut, addr, val)
  99             x = yield from read_from_addr(dut, addr << 2)
 100             print ("addr, val", addr, hex(val), hex(x))
 101             x = yield from read_byte(dut, addr)
 102             print ("addr, val", addr, hex(val), hex(x))
 103             assert x == val
 104
 105         values = [random.randint(0, (1<<32)-1) for x in range(16)]
 106
 107         for addr, val in enumerate(values):
 108             yield from write_to_addr(dut, addr << 2, val)
 109             x = yield from read_from_addr(dut, addr << 2)
 110             print ("addr, val", addr, hex(val), hex(x))
 111             assert x == val
 112
 113     sim.add_sync_process(process)
 114     with sim.write_vcd("test_loadstore_%s.vcd" % ifacetype, traces=[]):
 115         sim.run()
 116
 117 if __name__ == '__main__':
 118     tst_lsmemtype('test_bare_wb')
 119     tst_lsmemtype('testmem')