src/soc/config/test/test_loadstore.py

   1 from soc.minerva.units.loadstore import LoadStoreUnitInterface
   2 from nmigen import Signal, Module, Elaboratable, Mux
   3 from nmigen.utils import log2_int
   4 import random
   5 from nmigen.back.pysim import Simulator, Settle
   6 from soc.config.loadstore import ConfigLoadStoreUnit
   7 from collections import namedtuple
   8
   9
  10 def write_to_addr(dut, addr, value):
  11     yield dut.x_addr_i.eq(addr)
  12     yield dut.x_st_data_i.eq(value)
  13     yield dut.x_st_i.eq(1)
  14     yield dut.x_mask_i.eq(-1)
  15     yield dut.x_valid_i.eq(1)
  16     yield dut.x_stall_i.eq(1)
  17     yield
  18     yield
  19
  20     yield dut.x_stall_i.eq(0)
  21     yield
  22     yield dut.x_st_i.eq(0)
  23     while (yield dut.x_stall_i):
  24         yield
  25
  26
  27 def read_from_addr(dut, addr):
  28     yield dut.x_addr_i.eq(addr)
  29     yield dut.x_ld_i.eq(1)
  30     yield dut.x_valid_i.eq(1)
  31     yield dut.x_stall_i.eq(1)
  32     yield
  33     yield dut.x_stall_i.eq(0)
  34     yield
  35     yield dut.x_ld_i.eq(0)
  36     yield Settle()
  37     while (yield dut.x_stall_i):
  38         yield
  39     assert (yield dut.x_valid_i)
  40     return (yield dut.m_ld_data_o)
  41
  42
  43 def write_byte(dut, addr, val):
  44     offset = addr & 0x3
  45     yield dut.x_addr_i.eq(addr)
  46     yield dut.x_st_i.eq(1)
  47     yield dut.x_st_data_i.eq(val << (offset * 8))
  48     yield dut.x_mask_i.eq(1 << offset)
  49     yield dut.x_valid_i.eq(1)
  50
  51     yield
  52     yield dut.x_st_i.eq(0)
  53     while (yield dut.x_stall_i):
  54         yield
  55
  56
  57 def read_byte(dut, addr):
  58     offset = addr & 0x3
  59     yield dut.x_addr_i.eq(addr)
  60     yield dut.x_ld_i.eq(1)
  61     yield dut.x_valid_i.eq(1)
  62     yield
  63     yield dut.x_ld_i.eq(0)
  64     yield Settle()
  65     while (yield dut.x_stall_i):
  66         yield
  67     assert (yield dut.x_valid_i)
  68     val = (yield dut.m_ld_data_o)
  69     return (val >> (offset * 8)) & 0xff
  70
  71
  72 def tst_lsmemtype(ifacetype):
  73     m = Module()
  74     Pspec = namedtuple('Pspec', ['ldst_ifacetype',
  75                                  'addr_wid', 'mask_wid', 'reg_wid'])
  76     pspec = Pspec(ldst_ifacetype=ifacetype, addr_wid=64, mask_wid=4, reg_wid=64)
  77     dut = ConfigLoadStoreUnit(pspec).lsi
  78     m.submodules.dut = dut
  79
  80     sim = Simulator(m)
  81     sim.add_clock(1e-6)
  82
  83     def process():
  84
  85         values = [random.randint(0, (1<<32)-1) for x in range(16)]
  86
  87         for addr, val in enumerate(values):
  88             yield from write_to_addr(dut, addr << 2, val)
  89         for addr, val in enumerate(values):
  90             x = yield from read_from_addr(dut, addr << 2)
  91             assert x == val
  92
  93         values = [random.randint(0, 255) for x in range(16*4)]
  94         for addr, val in enumerate(values):
  95             yield from write_byte(dut, addr, val)
  96         for addr, val in enumerate(values):
  97             x = yield from read_byte(dut, addr)
  98             assert x == val
  99
 100     sim.add_sync_process(process)
 101     with sim.write_vcd("test_loadstore_%s.vcd" % ifacetype, traces=[]):
 102         sim.run()
 103
 104 if __name__ == '__main__':
 105     tst_lsmemtype('testmem')
 106     tst_lsmemtype('test_bare_wb')