src/soc/consts.py

   1 # sigh create little-ended versions of bitfield flags
   2 def botchify(bekls, lekls):
   3     for attr in dir(bekls):
   4         if attr[0] == '_':
   5             continue
   6         setattr(lekls, attr, 63-getattr(bekls, attr))
   7
   8
   9 # Can't think of a better place to put these functions.
  10 # Return an arbitrary subfield of a larger field.
  11 def field_slice(msb0_start, msb0_end, field_width=64):
  12     """field_slice
  13
  14     Answers with a subfield slice of the signal r ("register"),
  15     where the start and end bits use IBM "MSB 0" conventions.
  16
  17     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  18
  19     * assertion: msb0_start < msb0_end.
  20     * The range specified is inclusive on both ends.
  21     * field_width specifies the total number of bits (note: not bits-1)
  22     """
  23     if msb0_start >= msb0_end:
  24         raise ValueError(
  25             "start ({}) must be less than end ({})".format(msb0_start, msb0_end)
  26         )
  27     # sigh.  MSB0 (IBM numbering) is inverted.  converting to python
  28     # we *swap names* so as not to get confused by having "end, start"
  29     lsb0_end = (field_width-1) - msb0_start
  30     lsb0_start = (field_width-1) - msb0_end
  31
  32     return slice(lsb0_start, lsb0_end + 1)
  33
  34
  35 def field(r, msb0_start, msb0_end=None, field_width=64):
  36     """Answers with a subfield of the signal r ("register"), where
  37     the start and end bits use IBM conventions.  start < end, if
  38     end is provided.  The range specified is inclusive on both ends.
  39
  40     Answers with a subfield of the signal r ("register"),
  41     where the start and end bits use IBM "MSB 0" conventions.
  42     If end is not provided, a single bit subfield is returned.
  43
  44     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  45
  46     * assertion: msb0_start < msb0_end.
  47     * The range specified is inclusive on both ends.
  48     * field_width specifies the total number of bits (note: not bits-1)
  49
  50     Example usage:
  51
  52         comb += field(insn, 0, 6, field_width=32).eq(17)
  53         # NOTE: NEVER DIRECTLY ACCESS OPCODE FIELDS IN INSTRUCTIONS.
  54         # This example is purely for illustrative purposes only.
  55         # Use self.fields.FormXYZ.etcetc instead.
  56
  57         comb += field(msr, MSRb.TEs, MSRb.TEe).eq(0)
  58
  59     Proof by substitution:
  60
  61            field(insn, 0, 6, field_width=32).eq(17)
  62         == insn[field_slice(0, 6, field_width=32)].eq(17)
  63         == insn[slice((31-6), (31-0)+1)].eq(17)
  64         == insn[slice(25, 32)].eq(17)
  65         == insn[25:32].eq(17)
  66
  67            field(msr, MSRb.TEs, MSRb.TEe).eq(0)
  68         == field(msr, 53, 54).eq(0)
  69         == msr[field_slice(53, 54)].eq(0)
  70         == msr[slice((63-54), (63-53)+1)].eq(0)  # note cross-over!
  71         == msr[slice(9, 11)].eq(0)
  72         == msr[9:11].eq(0)
  73     """
  74     if msb0_end is None:
  75         return r[(field_width - 1) - msb0_start]
  76     else:
  77         return r[field_slice(msb0_start, msb0_end)]
  78
  79
  80 # Listed in V3.0B Book III Chap 4.2.1
  81 # MSR bit numbers, *bigendian* order (PowerISA format)
  82 # use this in the simulator
  83 class MSRb:
  84     SF  = 0     # Sixty-Four bit mode
  85     HV  = 3     # Hypervisor state
  86     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
  87     TSs = 29    # Transactional State (subfield)
  88     TSe = 30    # Transactional State (subfield)
  89     TM  = 31    # Transactional Memory Available
  90     VEC = 38    # Vector Available
  91     VSX = 40    # VSX Available
  92     S   = 41    # Secure state
  93     EE  = 48    # External interrupt Enable
  94     PR  = 49    # PRoblem state
  95     FP  = 50    # FP available
  96     ME  = 51    # Machine Check int enable
  97     FE0 = 52    # Floating-Point Exception Mode 0
  98     TEs = 53    # Trace Enable (subfield)
  99     TEe = 54    # Trace Enable (subfield)
 100     FE1 = 55    # Floating-Point Exception Mode 1
 101     IR  = 58    # Instruction Relocation
 102     DR  = 59    # Data Relocation
 103     PMM = 60    # Performance Monitor Mark
 104     RI  = 62    # Recoverable Interrupt
 105     LE  = 63    # Little Endian
 106
 107 # use this inside the HDL (where everything is little-endian)
 108 class MSR:
 109     pass
 110
 111 botchify(MSRb, MSR)
 112
 113 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
 114
 115 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
 116 # (TODO: add more?)
 117 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 118 # to expand traptype to cope with the increased range
 119
 120 # use this in the simulator
 121 class PIb:
 122     INVALID      = 33    # 1 for an invalid mem err
 123     PERMERR      = 35    # 1 for an permanent mem err
 124     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
 125     FP           = 43    # 1 if FP exception
 126     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
 127     PRIV         = 45    # 1 if privileged interrupt
 128     TRAP         = 46    # 1 if exception is "trap" type
 129     ADR          = 47    # 0 if SRR0 = address of instruction causing exception
 130
 131 # and use this in the HDL
 132 class PI:
 133     pass
 134
 135 botchify(PIb, PI)
 136
 137 # see traptype (and trap main_stage.py)
 138 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 139 # to expand traptype to cope with the increased range
 140
 141 class TT:
 142     FP = 1<<0
 143     PRIV = 1<<1
 144     TRAP = 1<<2
 145     ADDR = 1<<3
 146     EINT = 1<<4  # external interrupt
 147     DEC = 1<<5   # decrement counter
 148     MEMEXC = 1<<6 # LD/ST exception
 149     ILLEG = 1<<7 # currently the max
 150     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
 151     size = 8 # MUST update this to contain the full number of Trap Types