src/soc/consts.py

   1 # sigh create little-ended versions of bitfield flags
   2 from nmigen import Cat
   3
   4
   5 def botchify(bekls, lekls, msb=63):
   6     for attr in dir(bekls):
   7         if attr[0] == '_':
   8             continue
   9         setattr(lekls, attr, msb-getattr(bekls, attr))
  10
  11
  12 # Can't think of a better place to put these functions.
  13 # Return an arbitrary subfield of a larger field.
  14 def field_slice(msb0_start, msb0_end, field_width=64):
  15     """field_slice
  16
  17     Answers with a subfield slice of the signal r ("register"),
  18     where the start and end bits use IBM "MSB 0" conventions.
  19
  20     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  21
  22     * assertion: msb0_start < msb0_end.
  23     * The range specified is inclusive on both ends.
  24     * field_width specifies the total number of bits (note: not bits-1)
  25     """
  26     if msb0_start >= msb0_end:
  27         raise ValueError(
  28             "start ({}) must be less than end ({})".format(msb0_start, msb0_end)
  29         )
  30     # sigh.  MSB0 (IBM numbering) is inverted.  converting to python
  31     # we *swap names* so as not to get confused by having "end, start"
  32     lsb0_end = (field_width-1) - msb0_start
  33     lsb0_start = (field_width-1) - msb0_end
  34
  35     return slice(lsb0_start, lsb0_end + 1)
  36
  37
  38 def field(r, msb0_start, msb0_end=None, field_width=64):
  39     """Answers with a subfield of the signal r ("register"), where
  40     the start and end bits use IBM conventions.  start < end, if
  41     end is provided.  The range specified is inclusive on both ends.
  42
  43     Answers with a subfield of the signal r ("register"),
  44     where the start and end bits use IBM "MSB 0" conventions.
  45     If end is not provided, a single bit subfield is returned.
  46
  47     see: https://en.wikipedia.org/wiki/Bit_numbering#MSB_0_bit_numbering
  48
  49     * assertion: msb0_start < msb0_end.
  50     * The range specified is inclusive on both ends.
  51     * field_width specifies the total number of bits (note: not bits-1)
  52
  53     Example usage:
  54
  55         comb += field(insn, 0, 6, field_width=32).eq(17)
  56         # NOTE: NEVER DIRECTLY ACCESS OPCODE FIELDS IN INSTRUCTIONS.
  57         # This example is purely for illustrative purposes only.
  58         # Use self.fields.FormXYZ.etcetc instead.
  59
  60         comb += field(msr, MSRb.TEs, MSRb.TEe).eq(0)
  61
  62     Proof by substitution:
  63
  64            field(insn, 0, 6, field_width=32).eq(17)
  65         == insn[field_slice(0, 6, field_width=32)].eq(17)
  66         == insn[slice((31-6), (31-0)+1)].eq(17)
  67         == insn[slice(25, 32)].eq(17)
  68         == insn[25:32].eq(17)
  69
  70            field(msr, MSRb.TEs, MSRb.TEe).eq(0)
  71         == field(msr, 53, 54).eq(0)
  72         == msr[field_slice(53, 54)].eq(0)
  73         == msr[slice((63-54), (63-53)+1)].eq(0)  # note cross-over!
  74         == msr[slice(9, 11)].eq(0)
  75         == msr[9:11].eq(0)
  76     """
  77     if msb0_end is None:
  78         return r[(field_width - 1) - msb0_start]
  79     else:
  80         return r[field_slice(msb0_start, msb0_end, field_width)]
  81
  82
  83 # Listed in V3.0B Book III Chap 4.2.1
  84 # MSR bit numbers, *bigendian* order (PowerISA format)
  85 # use this in the simulator
  86 class MSRb:
  87     SF  = 0     # Sixty-Four bit mode
  88     HV  = 3     # Hypervisor state
  89     UND = 5     # Undefined behavior state (see Bk 2, Sect. 3.2.1)
  90     TSs = 29    # Transactional State (subfield)
  91     TSe = 30    # Transactional State (subfield)
  92     TM  = 31    # Transactional Memory Available
  93     VEC = 38    # Vector Available
  94     VSX = 40    # VSX Available
  95     S   = 41    # Secure state
  96     EE  = 48    # External interrupt Enable
  97     PR  = 49    # PRoblem state
  98     FP  = 50    # FP available
  99     ME  = 51    # Machine Check int enable
 100     FE0 = 52    # Floating-Point Exception Mode 0
 101     TEs = 53    # Trace Enable (subfield)
 102     TEe = 54    # Trace Enable (subfield)
 103     FE1 = 55    # Floating-Point Exception Mode 1
 104     IR  = 58    # Instruction Relocation
 105     DR  = 59    # Data Relocation
 106     PMM = 60    # Performance Monitor Mark
 107     RI  = 62    # Recoverable Interrupt
 108     LE  = 63    # Little Endian
 109
 110 # use this inside the HDL (where everything is little-endian)
 111 class MSR:
 112     pass
 113
 114 botchify(MSRb, MSR)
 115
 116 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
 117
 118 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
 119 # (TODO: add more?)
 120 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 121 # to expand traptype to cope with the increased range
 122
 123 # use this in the simulator
 124 class PIb:
 125     INVALID      = 33    # 1 for an invalid mem err
 126     PERMERR      = 35    # 1 for an permanent mem err
 127     TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
 128     FP           = 43    # 1 if FP exception
 129     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
 130     PRIV         = 45    # 1 if privileged interrupt
 131     TRAP         = 46    # 1 if exception is "trap" type
 132     ADR          = 47    # 0 if SRR0 = address of instruction causing exception
 133
 134 # and use this in the HDL
 135 class PI:
 136     pass
 137
 138 botchify(PIb, PI)
 139
 140 # see traptype (and trap main_stage.py)
 141 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
 142 # to expand traptype to cope with the increased range
 143
 144 class TT:
 145     FP = 1<<0
 146     PRIV = 1<<1
 147     TRAP = 1<<2
 148     ADDR = 1<<3
 149     EINT = 1<<4  # external interrupt
 150     DEC = 1<<5   # decrement counter
 151     MEMEXC = 1<<6 # LD/ST exception
 152     ILLEG = 1<<7 # currently the max
 153     # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
 154     size = 8 # MUST update this to contain the full number of Trap Types
 155
 156
 157 # EXTRA3 3-bit subfield (spec)
 158 class SPECb:
 159     VEC = 0  # 1 for vector, 0 for scalar
 160     MSB = 1  # augmented register number, MSB
 161     LSB = 2  # augmented register number, LSB
 162
 163
 164 SPEC_SIZE = 3
 165 SPEC_AUG_SIZE = 2  # augmented subfield size (MSB+LSB above)
 166 class SPEC:
 167     pass
 168 botchify(SPECb, SPEC, SPEC_SIZE-1)
 169
 170
 171 # EXTRA field, with EXTRA2 subfield encoding
 172 class EXTRA2b:
 173     IDX0_VEC = 0
 174     IDX0_MSB = 1
 175     IDX1_VEC = 2
 176     IDX1_MSB = 3
 177     IDX2_VEC = 4
 178     IDX2_MSB = 5
 179     IDX3_VEC = 6
 180     IDX3_MSB = 7
 181     RESERVED = 8
 182
 183
 184 EXTRA2_SIZE = 9
 185 class EXTRA2:
 186     pass
 187 botchify(EXTRA2b, EXTRA2, EXTRA2_SIZE-1)
 188
 189
 190 # EXTRA field, with EXTRA3 subfield encoding
 191 class EXTRA3:
 192     IDX0 = [0, 1, 2]
 193     IDX1 = [3, 4, 5]
 194     IDX2 = [6, 7, 8]
 195     MASK = [6, 7, 8]
 196
 197
 198 EXTRA3_SIZE = 9
 199
 200
 201 # SVP64 ReMapped Field (from v3.1 EXT001 Prefix)
 202 class SVP64P:
 203     OPC = range(0, 6)
 204     SVP64_7_9 = [7, 9]
 205     RM = [6, 8] + list(range(10, 32))
 206
 207 # 24 bits in RM
 208 SVP64P_SIZE = 24
 209
 210
 211 # CR SVP64 offsets
 212 class SVP64CROffs:
 213     CR0 = 0    # TODO: increase when CRs are expanded to 128
 214     CR1 = 1    # TODO: increase when CRs are expanded to 128
 215