1 # sigh create little-ended versions of bitfield flags
2 def botchify(bekls
, lekls
):
3 for attr
in dir(bekls
):
6 setattr(lekls
, attr
, 63-getattr(bekls
, attr
))
9 # Can't think of a better place to put these functions.
10 # Return an arbitrary subfield of a larger field.
11 def field_slice(start
, end
):
12 """Answers with a subfield slice of the signal r ("register"),
13 where the start and end bits use IBM conventions. start < end.
14 The range specified is inclusive on both ends.
18 # XXX must do the endian-reversing BEFORE doing the comparison
19 # if done after, that instead asserts that (after modification)
20 # start *MUST* be greater than end!
23 "start ({}) must be less than end ({})".format(start
, end
)
25 return slice(end
, start
+ 1)
28 def field(r
, start
, end
=None):
29 """Answers with a subfield of the signal r ("register"), where
30 the start and end bits use IBM conventions. start < end, if
31 end is provided. The range specified is inclusive on both ends.
36 return r
[field_slice(start
, end
)]
39 # Listed in V3.0B Book III Chap 4.2.1
40 # MSR bit numbers, *bigendian* order (PowerISA format)
41 # use this in the simulator
43 SF
= 0 # Sixty-Four bit mode
44 HV
= 3 # Hypervisor state
45 UND
= 5 # Undefined behavior state (see Bk 2, Sect. 3.2.1)
46 TSs
= 29 # Transactional State (subfield)
47 TSe
= 30 # Transactional State (subfield)
48 TM
= 31 # Transactional Memory Available
49 VEC
= 38 # Vector Available
50 VSX
= 40 # VSX Available
52 EE
= 48 # External interrupt Enable
53 PR
= 49 # PRoblem state
54 FP
= 50 # FP available
55 ME
= 51 # Machine Check int enable
56 FE0
= 52 # Floating-Point Exception Mode 0
57 TEs
= 53 # Trace Enable (subfield)
58 TEe
= 54 # Trace Enable (subfield)
59 FE1
= 55 # Floating-Point Exception Mode 1
60 IR
= 58 # Instruction Relocation
61 DR
= 59 # Data Relocation
62 PMM
= 60 # Performance Monitor Mark
63 RI
= 62 # Recoverable Interrupt
64 LE
= 63 # Little Endian
66 # use this inside the HDL (where everything is little-endian)
72 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
74 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
76 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
77 # to expand traptype to cope with the increased range
79 # use this in the simulator
81 TM_BAD_THING
= 42 # 1 for a TM Bad Thing type interrupt
82 FP
= 43 # 1 if FP exception
83 ILLEG
= 44 # 1 if illegal instruction (not doing hypervisor)
84 PRIV
= 45 # 1 if privileged interrupt
85 TRAP
= 46 # 1 if exception is "trap" type
86 ADR
= 47 # 0 if SRR0 = address of instruction causing exception
88 # and use this in the HDL
94 # see traptype (and trap main_stage.py)
95 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
96 # to expand traptype to cope with the increased range
103 ILLEG
= 1<<4 # currently the max, therefore traptype must be 5 bits
104 # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
105 size
= 5 # MUST update this to contain the full number of Trap Types