1 # sigh create little-ended versions of bitfield flags
2 def botchify(bekls
, lekls
):
3 for attr
in dir(bekls
):
6 setattr(lekls
, attr
, 63-getattr(bekls
, attr
))
8 # Listed in V3.0B Book III Chap 4.2.1
9 # MSR bit numbers, *bigendian* order (PowerISA format)
10 # use this in the simulator
12 SF
= 0 # Sixty-Four bit mode
13 HV
= 3 # Hypervisor state
14 UND
= 5 # Undefined behavior state (see Bk 2, Sect. 3.2.1)
15 TSs
= 29 # Transactional State (subfield)
16 TSe
= 30 # Transactional State (subfield)
17 TM
= 31 # Transactional Memory Available
18 VEC
= 38 # Vector Available
19 VSX
= 40 # VSX Available
21 EE
= 48 # External interrupt Enable
22 PR
= 49 # PRoblem state
23 FP
= 50 # FP available
24 ME
= 51 # Machine Check int enable
25 FE0
= 52 # Floating-Point Exception Mode 0
26 TEs
= 53 # Trace Enable (subfield)
27 TEe
= 54 # Trace Enable (subfield)
28 FE1
= 55 # Floating-Point Exception Mode 1
29 IR
= 58 # Instruction Relocation
30 DR
= 59 # Data Relocation
31 PMM
= 60 # Performance Monitor Mark
32 RI
= 62 # Recoverable Interrupt
33 LE
= 63 # Little Endian
35 # use this inside the HDL (where everything is little-endian)
41 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
43 # note that these correspond to trap_input_record.traptype bits 0,1,2,3,4
45 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
46 # to expand traptype to cope with the increased range
48 # use this in the simulator
50 TM_BAD_THING
= 42 # 1 for a TM Bad Thing type interrupt
51 FP
= 43 # 1 if FP exception
52 ILLEG
= 44 # 1 if illegal instruction (not doing hypervisor)
53 PRIV
= 45 # 1 if privileged interrupt
54 TRAP
= 46 # 1 if exception is "trap" type
55 ADR
= 47 # 0 if SRR0 = address of instruction causing exception
57 # and use this in the HDL
63 # see traptype (and trap main_stage.py)
64 # IMPORTANT: when adding extra bits here it is CRITICALLY IMPORTANT
65 # to expand traptype to cope with the increased range
72 ILLEG
= 1<<4 # currently the max, therefore traptype must be 5 bits
73 # TODO: support for TM_BAD_THING (not included yet in trap main_stage.py)
74 size
= 5 # MUST update this to contain the full number of Trap Types