src/soc/consts.py

   1 # Listed in V3.0B Book III Chap 4.2.1
   2 # MSR bit numbers
   3
   4 class MSR:
   5     SF  = (63 - 0)     # Sixty-Four bit mode
   6     HV  = (63 - 3)     # Hypervisor state
   7     S   = (63 - 41)    # Secure state
   8     EE  = (63 - 48)    # External interrupt Enable
   9     PR  = (63 - 49)    # PRoblem state
  10     FP  = (63 - 50)    # FP available
  11     ME  = (63 - 51)    # Machine Check int enable
  12     FE0 = (63 - 52)    # Floating-Point Exception Mode 0
  13     FE1 = (63 - 55)    # Floating-Point Exception Mode 1
  14     IR  = (63 - 58)    # Instruction Relocation
  15     DR  = (63 - 59)    # Data Relocation
  16     PMM = (63 - 60)    # Performance Monitor Mark
  17     RI  = (63 - 62)    # Recoverable Interrupt
  18     LE  = (63 - 63)    # Little Endian
  19
  20 # Listed in V3.0B Book III 7.5.9 "Program Interrupt"
  21
  22 # note that these correspond to trap_input_record.traptype bits 0,1,2,3
  23 # (TODO: add more?)
  24
  25 class PI:
  26     FP    = (63 - 43)    # 1 if FP exception
  27     ILLEG = (63 - 44)    # 1 if illegal instruction (not doing hypervisor)
  28     PRIV  = (63 - 45)    # 1 if privileged interrupt
  29     TRAP  = (63 - 46)    # 1 if exception is "trap" type
  30     ADR   = (63 - 47)    # 0 if SRR0 = address of instruction causing exception
  31
  32 # see traptype (and trap main_stage.py)
  33
  34 class TT:
  35     FP = 1<<0
  36     PRIV = 1<<1
  37     TRAP = 1<<2
  38     ADDR = 1<<3
  39     ILLEG = 1<<4