dcache: add debug output
[soc.git] / src / soc / debug / dmi.py
1 """Converted from microwatt core_debug.vhdl to nmigen
2
3 Provides a DMI (Debug Module Interface) for accessing a Libre-SOC core,
4 compatible with microwatt's same interface.
5
6 See constants below for addresses and register formats
7 """
8
9 from nmigen import Elaboratable, Module, Signal, Cat, Const, Record, Array, Mux
10 from nmutil.iocontrol import RecordObject
11 from nmigen.utils import log2_int
12 from nmigen.cli import rtlil
13 from soc.config.state import CoreState
14
15
16 # DMI register addresses
17 class DBGCore:
18 CTRL = 0b0000
19 STAT = 0b0001
20 NIA = 0b0010 # NIA register (read only for now)
21 MSR = 0b0011 # MSR (read only)
22 GSPR_IDX = 0b0100 # GSPR register index
23 GSPR_DATA = 0b0101 # GSPR register data
24 LOG_ADDR = 0b0110 # Log buffer address register
25 LOG_DATA = 0b0111 # Log buffer data register
26 CR = 0b1000 # CR (read only)
27 XER = 0b1001 # XER (read only) - note this is a TEMPORARY hack
28 SVSTATE = 0b1010 # SVSTATE register (read only for now)
29
30
31 # CTRL register (direct actions, write 1 to act, read back 0)
32 # bit 0 : Core stop
33 # bit 1 : Core reset (doesn't clear stop)
34 # bit 2 : Icache reset
35 # bit 3 : Single step
36 # bit 4 : Core start
37 class DBGCtrl:
38 STOP = 0
39 RESET = 1
40 ICRESET = 2
41 STEP = 3
42 START = 4
43
44
45 # STAT register (read only)
46 # bit 0 : Core stopping (wait til bit 1 set)
47 # bit 1 : Core stopped
48 # bit 2 : Core terminated (clears with start or reset)
49 class DBGStat:
50 STOPPING = 0
51 STOPPED = 1
52 TERM = 2
53
54
55 class DMIInterface(RecordObject):
56 def __init__(self, name=None):
57 super().__init__(name=name)
58 self.addr_i = Signal(4) # DMI register address
59 self.din = Signal(64) # DMI data write in (if we=1)
60 self.dout = Signal(64) # DMI data read out (if we=0)
61 self.req_i = Signal() # DMI request valid (stb)
62 self.we_i = Signal() # DMI write-enable
63 self.ack_o = Signal() # DMI ack request
64
65 def connect_to(self, other):
66 return [self.addr_i.eq(other.addr_i),
67 self.req_i.eq(other.req_i),
68 self.we_i.eq(other.we_i),
69 self.din.eq(other.din),
70 other.ack_o.eq(self.ack_o),
71 other.dout.eq(self.dout),
72 ]
73
74 class DbgReg(RecordObject):
75 def __init__(self, name):
76 super().__init__(name=name)
77 self.req = Signal()
78 self.ack = Signal()
79 self.addr = Signal(7) # includes fast SPRs, others?
80 self.data = Signal(64)
81
82
83 class DbgCRReg(RecordObject):
84 def __init__(self, name):
85 super().__init__(name=name)
86 self.req = Signal()
87 self.ack = Signal()
88 self.data = Signal(32)
89
90
91 class CoreDebug(Elaboratable):
92 def __init__(self, LOG_LENGTH=0): # TODO - debug log 512):
93 # Length of log buffer
94 self.LOG_LENGTH = LOG_LENGTH
95 self.dmi = DMIInterface("dmi")
96
97 # Debug actions
98 self.core_stop_o = Signal()
99 self.core_rst_o = Signal()
100 self.icache_rst_o = Signal()
101
102 # Core status inputs
103 self.terminate_i = Signal()
104 self.core_stopped_i = Signal()
105 self.state = CoreState("core_dbg")
106
107 # GSPR register read port
108 self.d_gpr = DbgReg("d_gpr")
109
110 # CR register read port
111 self.d_cr = DbgReg("d_cr")
112
113 # XER register read port
114 self.d_xer = DbgReg("d_xer")
115
116 # Core logging data
117 self.log_data_i = Signal(256)
118 self.log_read_addr_i = Signal(32)
119 self.log_read_data_o = Signal(64)
120 self.log_write_addr_o = Signal(32)
121
122 # Misc
123 self.terminated_o = Signal()
124
125 def elaborate(self, platform):
126
127 m = Module()
128 comb, sync = m.d.comb, m.d.sync
129 dmi, d_gpr, d_cr, d_xer, = self.dmi, self.d_gpr, self.d_cr, self.d_xer
130
131 # DMI needs fixing... make a one clock pulse
132 dmi_req_i_1 = Signal()
133
134 # Some internal wires
135 stat_reg = Signal(64)
136
137 # Some internal latches
138 stopping = Signal()
139 do_step = Signal()
140 do_reset = Signal()
141 do_icreset = Signal()
142 terminated = Signal()
143 do_gspr_rd = Signal()
144 gspr_index = Signal.like(d_gpr.addr)
145
146 log_dmi_addr = Signal(32)
147 log_dmi_data = Signal(64)
148 do_dmi_log_rd = Signal()
149 dmi_read_log_data = Signal()
150 dmi_read_log_data_1 = Signal()
151
152 LOG_INDEX_BITS = log2_int(self.LOG_LENGTH)
153
154 # Single cycle register accesses on DMI except for GSPR data
155 with m.Switch(dmi.addr_i):
156 with m.Case(DBGCore.GSPR_DATA):
157 comb += dmi.ack_o.eq(d_gpr.ack)
158 comb += d_gpr.req.eq(dmi.req_i)
159 with m.Case(DBGCore.CR):
160 comb += dmi.ack_o.eq(d_cr.ack)
161 comb += d_cr.req.eq(dmi.req_i)
162 with m.Case(DBGCore.XER):
163 comb += dmi.ack_o.eq(d_xer.ack)
164 comb += d_xer.req.eq(dmi.req_i)
165 with m.Default():
166 comb += dmi.ack_o.eq(dmi.req_i)
167
168 # Status register read composition (DBUG_CORE_STAT_xxx)
169 comb += stat_reg.eq(Cat(stopping, # bit 0
170 self.core_stopped_i, # bit 1
171 terminated)) # bit 2
172
173 # DMI read data mux
174 with m.Switch(dmi.addr_i):
175 with m.Case( DBGCore.STAT):
176 comb += dmi.dout.eq(stat_reg)
177 with m.Case( DBGCore.NIA):
178 comb += dmi.dout.eq(self.state.pc)
179 with m.Case( DBGCore.MSR):
180 comb += dmi.dout.eq(self.state.msr)
181 with m.Case( DBGCore.SVSTATE):
182 comb += dmi.dout.eq(self.state.svstate)
183 with m.Case( DBGCore.GSPR_DATA):
184 comb += dmi.dout.eq(d_gpr.data)
185 with m.Case( DBGCore.LOG_ADDR):
186 comb += dmi.dout.eq(Cat(log_dmi_addr, self.log_write_addr_o))
187 with m.Case( DBGCore.LOG_DATA):
188 comb += dmi.dout.eq(log_dmi_data)
189 with m.Case(DBGCore.CR):
190 comb += dmi.dout.eq(d_cr.data)
191 with m.Case(DBGCore.XER):
192 comb += dmi.dout.eq(d_xer.data)
193
194 # DMI writes
195 # Reset the 1-cycle "do" signals
196 sync += do_step.eq(0)
197 sync += do_reset.eq(0)
198 sync += do_icreset.eq(0)
199 sync += do_dmi_log_rd.eq(0)
200
201 # Edge detect on dmi_req_i for 1-shot pulses
202 sync += dmi_req_i_1.eq(dmi.req_i)
203 with m.If(dmi.req_i & ~dmi_req_i_1):
204 with m.If(dmi.we_i):
205 #sync += Display("DMI write to " & to_hstring(dmi_addr))
206
207 # Control register actions
208
209 # Core control
210 with m.If(dmi.addr_i == DBGCore.CTRL):
211 with m.If(dmi.din[DBGCtrl.RESET]):
212 sync += do_reset.eq(1)
213 sync += terminated.eq(0)
214 with m.If(dmi.din[DBGCtrl.STOP]):
215 sync += stopping.eq(1)
216 with m.If(dmi.din[DBGCtrl.STEP]):
217 sync += do_step.eq(1)
218 sync += terminated.eq(0)
219 with m.If(dmi.din[DBGCtrl.ICRESET]):
220 sync += do_icreset.eq(1)
221 with m.If(dmi.din[DBGCtrl.START]):
222 sync += stopping.eq(0)
223 sync += terminated.eq(0)
224
225 # GSPR address
226 with m.Elif(dmi.addr_i == DBGCore.GSPR_IDX):
227 sync += gspr_index.eq(dmi.din)
228
229 # Log address
230 with m.Elif(dmi.addr_i == DBGCore.LOG_ADDR):
231 sync += log_dmi_addr.eq(dmi.din)
232 sync += do_dmi_log_rd.eq(1)
233 with m.Else():
234 # sync += Display("DMI read from " & to_string(dmi_addr))
235 pass
236
237 with m.Elif(dmi_read_log_data_1 & ~dmi_read_log_data):
238 # Increment log_dmi_addr after end of read from DBGCore.LOG_DATA
239 lds = log_dmi_addr[:LOG_INDEX_BITS+2]
240 sync += lds.eq(lds + 1)
241 sync += do_dmi_log_rd.eq(1)
242
243 sync += dmi_read_log_data_1.eq(dmi_read_log_data)
244 sync += dmi_read_log_data.eq(dmi.req_i &
245 (dmi.addr_i == DBGCore.LOG_DATA))
246
247 # Set core stop on terminate. We'll be stopping some time *after*
248 # the offending instruction, at least until we can do back flushes
249 # that preserve NIA which we can't just yet.
250 with m.If(self.terminate_i):
251 sync += stopping.eq(1)
252 sync += terminated.eq(1)
253
254 comb += d_gpr.addr.eq(gspr_index)
255
256 # Core control signals generated by the debug module
257 comb += self.core_stop_o.eq(stopping & ~do_step)
258 comb += self.core_rst_o.eq(do_reset)
259 comb += self.icache_rst_o.eq(do_icreset)
260 comb += self.terminated_o.eq(terminated)
261
262 # Logging RAM (none)
263
264 if self.LOG_LENGTH == 0:
265 self.log_read_data_o.eq(0)
266 self.log_write_addr_o.eq(0x00000001)
267
268 return m
269
270 # TODO: debug logging
271 """
272 maybe_log: with m.If(LOG_LENGTH > 0 generate
273 subtype log_ptr_t is unsigned(LOG_INDEX_BITS - 1 downto 0)
274 type log_array_t is array(0 to LOG_LENGTH - 1) of std_ulogic_vector(255 downto 0)
275 signal log_array : log_array_t
276 signal log_rd_ptr : log_ptr_t
277 signal log_wr_ptr : log_ptr_t
278 signal log_toggle = Signal()
279 signal log_wr_enable = Signal()
280 signal log_rd_ptr_latched : log_ptr_t
281 signal log_rd = Signal()_vector(255 downto 0)
282 signal log_dmi_reading = Signal()
283 signal log_dmi_read_done = Signal()
284
285 function select_dword(data = Signal()_vector(255 downto 0)
286 addr = Signal()_vector(31 downto 0)) return std_ulogic_vector is
287 variable firstbit : integer
288 begin
289 firstbit := to_integer(unsigned(addr(1 downto 0))) * 64
290 return data(firstbit + 63 downto firstbit)
291 end
292
293 attribute ram_style : string
294 attribute ram_style of log_array : signal is "block"
295 attribute ram_decomp : string
296 attribute ram_decomp of log_array : signal is "power"
297
298 begin
299 # Use MSB of read addresses to stop the logging
300 log_wr_enable.eq(not (self.log_read_addr(31) or log_dmi_addr(31))
301
302 log_ram: process(clk)
303 begin
304 with m.If(rising_edge(clk)):
305 with m.If(log_wr_enable = '1'):
306 log_array(to_integer(log_wr_ptr)).eq(self.log_data
307 end if
308 log_rd.eq(log_array(to_integer(log_rd_ptr_latched))
309 end if
310 end process
311
312
313 log_buffer: process(clk)
314 variable b : integer
315 variable data = Signal()_vector(255 downto 0)
316 begin
317 with m.If(rising_edge(clk)):
318 with m.If(rst = '1'):
319 log_wr_ptr.eq((others => '0')
320 log_toggle.eq('0'
321 with m.Elif(log_wr_enable = '1'):
322 with m.If(log_wr_ptr = to_unsigned(LOG_LENGTH - 1, LOG_INDEX_BITS)):
323 log_toggle.eq(not log_toggle
324 end if
325 log_wr_ptr.eq(log_wr_ptr + 1
326 end if
327 with m.If(do_dmi_log_rd = '1'):
328 log_rd_ptr_latched.eq(unsigned(log_dmi_addr(LOG_INDEX_BITS + 1 downto 2))
329 else
330 log_rd_ptr_latched.eq(unsigned(self.log_read_addr(LOG_INDEX_BITS + 1 downto 2))
331 end if
332 with m.If(log_dmi_read_done = '1'):
333 log_dmi_data.eq(select_dword(log_rd, log_dmi_addr)
334 else
335 self.log_read_data.eq(select_dword(log_rd, self.log_read_addr)
336 end if
337 log_dmi_read_done.eq(log_dmi_reading
338 log_dmi_reading.eq(do_dmi_log_rd
339 end if
340 end process
341 self.log_write_addr(LOG_INDEX_BITS - 1 downto 0).eq(std_ulogic_vector(log_wr_ptr)
342 self.log_write_addr(LOG_INDEX_BITS).eq('1'
343 self.log_write_addr(31 downto LOG_INDEX_BITS + 1).eq((others => '0')
344 end generate
345
346 """
347
348 def __iter__(self):
349 yield from self.dmi
350 yield self.core_stop_o
351 yield self.core_rst_o
352 yield self.icache_rst_o
353 yield self.terminate_i
354 yield self.core_stopped_i
355 yield from self.state
356 yield from self.d_gpr
357 yield from self.d_cr
358 yield from self.d_xer
359 yield self.log_data_i
360 yield self.log_read_addr_i
361 yield self.log_read_data_o
362 yield self.log_write_addr_o
363 yield self.terminated_o
364
365 def ports(self):
366 return list(self)
367
368
369 def test_debug():
370
371 dut = CoreDebug()
372 vl = rtlil.convert(dut, ports=dut.ports())
373 with open("test_core_debug.il", "w") as f:
374 f.write(vl)
375
376 if __name__ == '__main__':
377 test_debug()
378