src/soc/debug/dmi2jtag.py

   1 """DMI 2 JTAG
   2
   3 based on Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 from nmigen import (Module, Signal, Elaboratable, Const)
   7 from nmigen.cli import rtlil
   8 from c4m.nmigen.jtag.tap import TAP, IOType
   9
  10 from soc.bus.sram import SRAM
  11 from nmigen import Memory, Signal, Module
  12
  13 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
  14 from nmutil.util import wrap
  15
  16
  17 # JTAG to DMI interface
  18 #
  19 # DMI bus
  20 #
  21 #  clk : |   |   |   |    | | |
  22 #  req : ____/------------\_____
  23 #  addr: xxxx<            >xxxxx
  24 #  dout: xxxx<            >xxxxx
  25 #  wr  : xxxx<            >xxxxx
  26 #  din : xxxxxxxxxxxx<      >xxx
  27 #  ack : ____________/------\___
  28 #
  29 #  * addr/dout set along with req, can be latched on same cycle by slave
  30 #  * ack & din remain up until req is dropped by master, the slave must
  31 #    provide a stable output on din on reads during that time.
  32 #  * req remains low at until at least one sysclk after ack seen down.
  33
  34
  35 class DMITAP(TAP):
  36
  37     def external_ports(self):
  38         return [self.bus.tdo, self.bus.tdi, self.bus.tms, self.bus.tck]
  39
  40
  41 if __name__ == '__main__':
  42     dut = DMITAP(ir_width=4)
  43     iotypes = (IOType.In, IOType.Out, IOType.TriOut, IOType.InTriOut)
  44     ios = [dut.add_io(iotype=iotype) for iotype in iotypes]
  45     dut.sr = dut.add_shiftreg(ircode=4, length=3) # test loopback register
  46
  47     # create and connect wishbone SRAM (a quick way to do WB test)
  48     dut.wb = dut.add_wishbone(ircodes=[5, 6, 7], features={'err'},
  49                                address_width=16, data_width=16)
  50
  51     # create DMI2JTAG (goes through to dmi_sim())
  52     dut.dmi = dut.add_dmi(ircodes=[8, 9, 10])
  53
  54     vl = rtlil.convert(dut)
  55     with open("test_dmi2jtag.il", "w") as f:
  56         f.write(vl)
  57