5fe2c4caa6cedb0a5803d853098aed78394ef48f
1 """JTAG Wishbone firmware upload program
3 to test, run "python3 debug/test/test_jtag_tap_srv.py server"
8 from nmigen
import (Module
, Signal
, Elaboratable
, Const
)
9 from c4m
.nmigen
.jtag
.tap
import TAP
, IOType
10 from c4m
.nmigen
.jtag
.bus
import Interface
as JTAGInterface
11 from soc
.debug
.dmi
import DMIInterface
, DBGCore
12 from soc
.debug
.test
.dmi_sim
import dmi_sim
13 from soc
.debug
.jtag
import JTAG
14 from soc
.debug
.test
.jtagremote
import JTAGServer
, JTAGClient
16 from nmigen_soc
.wishbone
.sram
import SRAM
17 from nmigen
import Memory
, Signal
, Module
19 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
, Tick
20 from nmutil
.util
import wrap
21 from soc
.debug
.jtagutils
import (jtag_read_write_reg
,
22 jtag_srv
, jtag_set_reset
,
23 jtag_set_ir
, jtag_set_get_dr
)
27 # in, out, tri-out, tri-inout
28 'test': ['io0-', 'io1+', 'io2>', 'io3*'],
32 # JTAG-ircodes for accessing DMI
37 # JTAG-ircodes for accessing Wishbone
42 # JTAG boundary scan reg addresses
49 def jtag_sim(dut
, firmware
):
51 ####### JTAGy stuff (IDCODE) ######
54 yield from jtag_set_reset(dut
)
55 idcode
= yield from jtag_read_write_reg(dut
, 0b1, 32)
56 print ("idcode", hex(idcode
))
57 assert idcode
== 0x18ff
59 ####### JTAG to DMI ######
62 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, DBGCore
.CTRL
)
64 # read DMI CTRL register
65 status
= yield from jtag_read_write_reg(dut
, DMI_READ
, 64)
66 print ("dmi ctrl status", hex(status
))
70 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, 0)
72 # write DMI CTRL register
73 status
= yield from jtag_read_write_reg(dut
, DMI_WRRD
, 64, 0b101)
74 print ("dmi ctrl status", hex(status
))
75 assert status
== 4 # returned old value (nice! cool feature!)
78 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, DBGCore
.CTRL
)
80 # read DMI CTRL register
81 status
= yield from jtag_read_write_reg(dut
, DMI_READ
, 64)
82 print ("dmi ctrl status", hex(status
))
85 # write DMI MSR address
86 yield from jtag_read_write_reg(dut
, DMI_ADDR
, 8, DBGCore
.MSR
)
88 # read DMI MSR register
89 msr
= yield from jtag_read_write_reg(dut
, DMI_READ
, 64)
90 print ("dmi msr", hex(msr
))
91 assert msr
== 0xdeadbeef
93 ####### JTAG to Wishbone ######
95 # write Wishbone address
96 yield from jtag_read_write_reg(dut
, WB_ADDR
, 64, 0)
98 # write/read wishbone data
100 data
= yield from jtag_read_write_reg(dut
, WB_WRRD
, 64, val
)
101 print ("wb write", hex(data
))
103 # write Wishbone address
104 yield from jtag_read_write_reg(dut
, WB_ADDR
, 64, 0)
106 # confirm data written
108 data
= yield from jtag_read_write_reg(dut
, WB_READ
, 64, 0)
109 print ("wb read", hex(data
))
111 ####### done - tell dmi_sim to stop (otherwise it won't) ########
113 print ("jtag sim stopping")
116 if __name__
== '__main__':
117 # rather than the client access the JTAG bus directly
118 # create an alternative that the client sets
121 cdut
.cbus
= JTAGInterface()
123 # set up client-server on port 44843-something
124 cdut
.c
= JTAGClient()
126 # take copy of ir_width and scan_len
131 m
.d
.sync
+= flag
.eq(~flag
) # get us a "sync" domain
134 sim
.add_clock(1e-6, domain
="sync") # standard clock
136 data
= [0x01, 0x02] # list of 64-bit words
137 sim
.add_sync_process(wrap(jtag_sim(cdut
, data
)))
139 with sim
.write_vcd("jtag_firmware_upload.vcd"):