src/soc/debug/jtag.py

   1 """JTAG interface
   2
   3 using Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 from collections import OrderedDict
   7 from nmigen import (Module, Signal, Elaboratable)
   8 from nmigen.cli import rtlil
   9 from c4m.nmigen.jtag.tap import IOType
  10 from soc.debug.dmi import  DMIInterface, DBGCore
  11 from soc.debug.dmi2jtag import DMITAP
  12
  13 # map from pinmux to c4m jtag iotypes
  14 iotypes = {'-': IOType.In,
  15            '+': IOType.Out,
  16            '*': IOType.InTriOut,
  17         }
  18
  19 scanlens = {IOType.In: 1,
  20            IOType.Out: 1,
  21            IOType.InTriOut: 3,
  22             }
  23
  24 def dummy_pinset():
  25     # sigh this needs to come from pinmux.
  26     gpios = []
  27     for i in range(16):
  28         gpios.append("gpio%d*" % i)
  29     return {'uart': ['tx+', 'rx-'],
  30              'gpio': gpios,
  31              'i2c': ['sda*', 'scl+']}
  32
  33 # TODO: move to suitable location
  34 class Pins:
  35     """declare a list of pins, including name and direction.  grouped by fn
  36     the pin dictionary needs to be in a reliable order so that the JTAG
  37     Boundary Scan is also in a reliable order
  38     """
  39     def __init__(self, pindict):
  40         self.io_names = OrderedDict()
  41         if isinstance(pindict, OrderedDict):
  42             self.io_names.update(pindict)
  43         else:
  44             keys = list(pindict.keys())
  45             keys.sort()
  46             for k in keys:
  47                 self.io_names[k] = pindict[k]
  48
  49     def __iter__(self):
  50         # start parsing io_names and enumerate them to return pin specs
  51         scan_idx = 0
  52         for fn, pins in self.io_names.items():
  53             for pin in pins:
  54                 # decode the pin name and determine the c4m jtag io type
  55                 name, pin_type = pin[:-1], pin[-1]
  56                 iotype = iotypes[pin_type]
  57                 pin_name = "%s_%s" % (fn, name)
  58                 yield (fn, name, iotype, pin_name, scan_idx)
  59                 scan_idx += scanlens[iotype] # inc boundary reg scan offset
  60
  61
  62 class JTAG(DMITAP, Pins):
  63     def __init__(self, pinset):
  64         DMITAP.__init__(self, ir_width=4)
  65         Pins.__init__(self, pinset)
  66
  67         # enumerate pin specs and create IOConn Records.
  68         # we store the boundary scan register offset in the IOConn record
  69         self.ios = [] # these are enumerated in external_ports
  70         for fn, pin, iotype, pin_name, scan_idx in list(self):
  71             io = self.add_io(iotype=iotype, name=pin_name)
  72             io._scan_idx = scan_idx # hmm shouldn't really do this
  73             self.ios.append(io)
  74
  75         # this is redundant.  or maybe part of testing, i don't know.
  76         self.sr = self.add_shiftreg(ircode=4, length=3)
  77
  78         # create and connect wishbone
  79         self.wb = self.add_wishbone(ircodes=[5, 6, 7],
  80                                    address_width=29, data_width=64,
  81                                    name="jtag_wb")
  82
  83         # create DMI2JTAG (goes through to dmi_sim())
  84         self.dmi = self.add_dmi(ircodes=[8, 9, 10])
  85
  86     def elaborate(self, platform):
  87         m = super().elaborate(platform)
  88         m.d.comb += self.sr.i.eq(self.sr.o) # loopback as part of test?
  89         return m
  90
  91     def external_ports(self):
  92         """create a list of ports that goes into the top level il (or verilog)
  93         """
  94         ports = super().external_ports()           # gets JTAG signal names
  95         ports += list(self.wb.fields.values())     # wishbone signals
  96         for io in self.ios:
  97             ports += list(io.core.fields.values()) # io "core" signals
  98             ports += list(io.pad.fields.values())  # io "pad" signals"
  99         return ports
 100
 101
 102 if __name__ == '__main__':
 103     pinset = dummy_pinset()
 104     dut = JTAG(pinset)
 105
 106     vl = rtlil.convert(dut)
 107     with open("test_jtag.il", "w") as f:
 108         f.write(vl)
 109