dcache: add debug output
[soc.git] / src / soc / debug / jtag.py
1 """JTAG interface
2
3 using Staf Verhaegen (Chips4Makers) wishbone TAP
4 """
5
6 from collections import OrderedDict
7 from nmigen import (Module, Signal, Elaboratable, Cat)
8 from nmigen.cli import rtlil
9 from c4m.nmigen.jtag.tap import IOType
10 from soc.debug.dmi import DMIInterface, DBGCore
11 from soc.debug.dmi2jtag import DMITAP
12
13 # map from pinmux to c4m jtag iotypes
14 iotypes = {'-': IOType.In,
15 '+': IOType.Out,
16 '>': IOType.TriOut,
17 '*': IOType.InTriOut,
18 }
19
20 scanlens = {IOType.In: 1,
21 IOType.Out: 1,
22 IOType.TriOut: 2,
23 IOType.InTriOut: 3,
24 }
25
26 def dummy_pinset():
27 # sigh this needs to come from pinmux.
28 gpios = []
29 for i in range(16):
30 gpios.append("%d*" % i)
31 return {'uart': ['tx+', 'rx-'],
32 'gpio': gpios,
33 'i2c': ['sda*', 'scl+']}
34
35 # TODO: move to suitable location
36 class Pins:
37 """declare a list of pins, including name and direction. grouped by fn
38 the pin dictionary needs to be in a reliable order so that the JTAG
39 Boundary Scan is also in a reliable order
40 """
41 def __init__(self, pindict):
42 self.io_names = OrderedDict()
43 if isinstance(pindict, OrderedDict):
44 self.io_names.update(pindict)
45 else:
46 keys = list(pindict.keys())
47 keys.sort()
48 for k in keys:
49 self.io_names[k] = pindict[k]
50
51 def __iter__(self):
52 # start parsing io_names and enumerate them to return pin specs
53 scan_idx = 0
54 for fn, pins in self.io_names.items():
55 for pin in pins:
56 # decode the pin name and determine the c4m jtag io type
57 name, pin_type = pin[:-1], pin[-1]
58 iotype = iotypes[pin_type]
59 pin_name = "%s_%s" % (fn, name)
60 yield (fn, name, iotype, pin_name, scan_idx)
61 scan_idx += scanlens[iotype] # inc boundary reg scan offset
62
63
64 class JTAG(DMITAP, Pins):
65 # 32-bit data width here so that it matches with litex
66 def __init__(self, pinset, domain, wb_data_wid=32):
67 self.domain = domain
68 DMITAP.__init__(self, ir_width=4)
69 Pins.__init__(self, pinset)
70
71 # enumerate pin specs and create IOConn Records.
72 # we store the boundary scan register offset in the IOConn record
73 self.ios = [] # these are enumerated in external_ports
74 self.scan_len = 0
75 for fn, pin, iotype, pin_name, scan_idx in list(self):
76 io = self.add_io(iotype=iotype, name=pin_name)
77 io._scan_idx = scan_idx # hmm shouldn't really do this
78 self.scan_len += scan_idx # record full length of boundary scan
79 self.ios.append(io)
80
81 # this is redundant. or maybe part of testing, i don't know.
82 self.sr = self.add_shiftreg(ircode=4, length=3,
83 domain=domain)
84
85 # create and connect wishbone
86 self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
87 address_width=30, data_width=wb_data_wid,
88 granularity=8, # 8-bit wide
89 name="jtag_wb",
90 domain=domain)
91
92 # create DMI2JTAG (goes through to dmi_sim())
93 self.dmi = self.add_dmi(ircodes=[8, 9, 10],
94 domain=domain)
95
96 # use this for enable/disable of parts of the ASIC.
97 # XXX make sure to add the _en sig to en_sigs list
98 self.wb_icache_en = Signal(reset=1)
99 self.wb_dcache_en = Signal(reset=1)
100 self.wb_sram_en = Signal(reset=1)
101 self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
102 self.wb_sram_en)
103 self.sr_en = self.add_shiftreg(ircode=11, length=len(en_sigs),
104 domain=domain)
105
106 def elaborate(self, platform):
107 m = super().elaborate(platform)
108 m.d.comb += self.sr.i.eq(self.sr.o) # loopback as part of test?
109
110 # provide way to enable/disable wishbone caches and SRAM
111 # just in case of issues
112 # see https://bugs.libre-soc.org/show_bug.cgi?id=520
113 with m.If(self.sr_en.oe):
114 m.d.sync += self.en_sigs.eq(self.sr_en.o)
115 # also make it possible to read the enable/disable current state
116 with m.If(self.sr_en.ie):
117 m.d.comb += self.sr_en.i.eq(self.en_sigs)
118
119 # create a fake "stall"
120 #wb = self.wb
121 #m.d.comb += wb.stall.eq(wb.cyc & ~wb.ack) # No burst support
122
123 return m
124
125 def external_ports(self):
126 """create a list of ports that goes into the top level il (or verilog)
127 """
128 ports = super().external_ports() # gets JTAG signal names
129 ports += list(self.wb.fields.values()) # wishbone signals
130 for io in self.ios:
131 ports += list(io.core.fields.values()) # io "core" signals
132 ports += list(io.pad.fields.values()) # io "pad" signals"
133 return ports
134
135
136 if __name__ == '__main__':
137 pinset = dummy_pinset()
138 dut = JTAG(pinset)
139
140 vl = rtlil.convert(dut)
141 with open("test_jtag.il", "w") as f:
142 f.write(vl)
143