JTAG boundary scan test 1st attempt
[soc.git] / src / soc / debug / test / test_jtag_tap_srv.py
1 """DMI 2 JTAG test
2
3 based on Staf Verhaegen (Chips4Makers) wishbone TAP
4 """
5
6 import sys
7 from nmigen import (Module, Signal, Elaboratable, Const)
8 from c4m.nmigen.jtag.tap import TAP, IOType
9 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
10 from soc.debug.dmi import DMIInterface, DBGCore
11 from soc.debug.test.dmi_sim import dmi_sim
12 from soc.debug.jtag import JTAG
13 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
14
15 from nmigen_soc.wishbone.sram import SRAM
16 from nmigen import Memory, Signal, Module
17
18 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
19 from nmutil.util import wrap
20 from soc.debug.jtagutils import (jtag_read_write_reg,
21 jtag_srv, jtag_set_reset,
22 jtag_set_ir, jtag_set_get_dr)
23
24 def test_pinset():
25 return {
26 # in, out, tri-out, tri-inout
27 'test': ['io0-', 'io1+', 'io2>', 'io3*'],
28 }
29
30
31 # JTAG-ircodes for accessing DMI
32 DMI_ADDR = 8
33 DMI_READ = 9
34 DMI_WRRD = 10
35
36 # JTAG-ircodes for accessing Wishbone
37 WB_ADDR = 5
38 WB_READ = 6
39 WB_WRRD = 7
40
41 # JTAG boundary scan reg addresses
42 BS_EXTEST = 0
43 BS_INTEST = 0
44 BS_SAMPLE = 2
45 BS_PRELOAD = 2
46
47
48 def jtag_sim(dut, srv_dut):
49
50 ####### JTAGy stuff (IDCODE) ######
51
52 # read idcode
53 yield from jtag_set_reset(dut)
54 idcode = yield from jtag_read_write_reg(dut, 0b1, 32)
55 print ("idcode", hex(idcode))
56 assert idcode == 0x18ff
57
58 ####### JTAG Boundary scan ######
59
60 bslen = dut.scan_len
61 print ("scan len", bslen)
62
63 # sample test
64 bs_actual = 0b100110
65 yield srv_dut.ios[0].pad.i.eq(1)
66 yield srv_dut.ios[1].core.o.eq(0)
67 yield srv_dut.ios[2].core.o.eq(1)
68 yield srv_dut.ios[2].core.oe.eq(1)
69 yield srv_dut.ios[3].pad.i.eq(0)
70 yield srv_dut.ios[3].core.o.eq(0)
71 yield srv_dut.ios[3].core.oe.eq(1)
72
73 bs = yield from jtag_read_write_reg(dut, BS_SAMPLE, bslen, bs_actual)
74 print ("bs scan", bin(bs))
75
76 print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
77 print ("io1 core.o", (yield srv_dut.ios[1].core.o))
78 print ("io2 core.o", (yield srv_dut.ios[2].core.o))
79 print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
80 print ("io3 core.i", (yield srv_dut.ios[3].core.i))
81 print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
82 print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
83
84 # extest
85 ir_actual = yield from jtag_set_ir(dut, BS_EXTEST)
86 print ("ir extest", bin(ir_actual))
87
88 print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
89 print ("io1 core.o", (yield srv_dut.ios[1].core.o))
90 print ("io2 core.o", (yield srv_dut.ios[2].core.o))
91 print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
92 print ("io3 core.i", (yield srv_dut.ios[3].core.i))
93 print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
94 print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
95
96 # set pins
97 bs_actual = 0b1011001
98 yield srv_dut.ios[0].pad.i.eq(0)
99 yield srv_dut.ios[1].core.o.eq(1)
100 yield srv_dut.ios[2].core.o.eq(0)
101 yield srv_dut.ios[2].core.oe.eq(0)
102 yield srv_dut.ios[3].pad.i.eq(1)
103 yield srv_dut.ios[3].core.o.eq(1)
104 yield srv_dut.ios[3].core.oe.eq(0)
105
106 bs = yield from jtag_set_get_dr(dut, bslen, bs_actual)
107 print ("bs scan", bin(bs))
108
109 print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
110 print ("io1 core.o", (yield srv_dut.ios[1].core.o))
111 print ("io2 core.o", (yield srv_dut.ios[2].core.o))
112 print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
113 print ("io3 core.i", (yield srv_dut.ios[3].core.i))
114 print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
115 print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
116
117 # reset
118 yield from jtag_set_reset(dut)
119 print ("bs reset")
120
121 print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
122 print ("io1 core.o", (yield srv_dut.ios[1].core.o))
123 print ("io2 core.o", (yield srv_dut.ios[2].core.o))
124 print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
125 print ("io3 core.i", (yield srv_dut.ios[3].core.i))
126 print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
127 print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
128
129 ####### JTAG to DMI ######
130
131 # write DMI address
132 yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
133
134 # read DMI CTRL register
135 status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
136 print ("dmi ctrl status", hex(status))
137 assert status == 4
138
139 # write DMI address
140 yield from jtag_read_write_reg(dut, DMI_ADDR, 8, 0)
141
142 # write DMI CTRL register
143 status = yield from jtag_read_write_reg(dut, DMI_WRRD, 64, 0b101)
144 print ("dmi ctrl status", hex(status))
145 assert status == 4 # returned old value (nice! cool feature!)
146
147 # write DMI address
148 yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
149
150 # read DMI CTRL register
151 status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
152 print ("dmi ctrl status", hex(status))
153 assert status == 5
154
155 # write DMI MSR address
156 yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR)
157
158 # read DMI MSR register
159 msr = yield from jtag_read_write_reg(dut, DMI_READ, 64)
160 print ("dmi msr", hex(msr))
161 assert msr == 0xdeadbeef
162
163 ####### JTAG to Wishbone ######
164
165 # write Wishbone address
166 yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
167
168 # write/read wishbone data
169 data = yield from jtag_read_write_reg(dut, WB_WRRD, 64, 0xfeef)
170 print ("wb write", hex(data))
171
172 # write Wishbone address
173 yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
174
175 # write/read wishbone data
176 data = yield from jtag_read_write_reg(dut, WB_READ, 64, 0)
177 print ("wb read", hex(data))
178
179 ####### done - tell dmi_sim to stop (otherwise it won't) ########
180
181 srv_dut.stop = True
182 print ("jtag sim stopping")
183
184
185 if __name__ == '__main__':
186 dut = JTAG(test_pinset(), wb_data_wid=64)
187 dut.stop = False
188
189 # rather than the client access the JTAG bus directly
190 # create an alternative that the client sets
191 class Dummy: pass
192 cdut = Dummy()
193 cdut.cbus = JTAGInterface()
194
195 # set up client-server on port 44843-something
196 dut.s = JTAGServer()
197 if len(sys.argv) != 2 or sys.argv[1] != 'server':
198 cdut.c = JTAGClient()
199 dut.s.get_connection()
200 else:
201 dut.s.get_connection(None) # block waiting for connection
202
203 # take copy of ir_width and scan_len
204 cdut._ir_width = dut._ir_width
205 cdut.scan_len = dut.scan_len
206
207 memory = Memory(width=64, depth=16)
208 sram = SRAM(memory=memory, bus=dut.wb)
209
210 m = Module()
211 m.submodules.ast = dut
212 m.submodules.sram = sram
213
214 sim = Simulator(m)
215 sim.add_clock(1e-6, domain="sync") # standard clock
216
217 sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server
218 if len(sys.argv) != 2 or sys.argv[1] != 'server':
219 sim.add_sync_process(wrap(jtag_sim(cdut, dut))) # actual jtag tester
220 else:
221 print ("running server only as requested, use openocd remote to test")
222 sim.add_sync_process(wrap(dmi_sim(dut))) # handles (pretends to be) DMI
223
224 with sim.write_vcd("dmi2jtag_test_srv.vcd"):
225 sim.run()