src/soc/debug/test/test_jtag_tap_srv.py

   1 """DMI 2 JTAG test
   2
   3 based on Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 import sys
   7 from nmigen import (Module, Signal, Elaboratable, Const)
   8 from c4m.nmigen.jtag.tap import TAP, IOType
   9 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
  10 from soc.debug.dmi import DMIInterface, DBGCore
  11 from soc.debug.test.dmi_sim import dmi_sim
  12 from soc.debug.jtag import JTAG, dummy_pinset
  13 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
  14
  15 from nmigen_soc.wishbone.sram import SRAM
  16 from nmigen import Memory, Signal, Module
  17
  18 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
  19 from nmutil.util import wrap
  20 from soc.debug.jtagutils import (jtag_read_write_reg,
  21                                  jtag_srv, jtag_set_reset)
  22
  23 # JTAG-ircodes for accessing DMI
  24 DMI_ADDR = 8
  25 DMI_READ = 9
  26 DMI_WRRD = 10
  27
  28 # JTAG-ircodes for accessing Wishbone
  29 WB_ADDR = 5
  30 WB_READ = 6
  31 WB_WRRD = 7
  32
  33
  34 def jtag_sim(dut, srv_dut):
  35
  36     ####### JTAGy stuff (IDCODE) ######
  37
  38     # read idcode
  39     yield from jtag_set_reset(dut)
  40     idcode = yield from jtag_read_write_reg(dut, 0b1, 32)
  41     print ("idcode", hex(idcode))
  42     assert idcode == 0x18ff
  43
  44     ####### JTAG to DMI ######
  45
  46     # write DMI address
  47     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
  48
  49     # read DMI CTRL register
  50     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
  51     print ("dmi ctrl status", hex(status))
  52     assert status == 4
  53
  54     # write DMI address
  55     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, 0)
  56
  57     # write DMI CTRL register
  58     status = yield from jtag_read_write_reg(dut, DMI_WRRD, 64, 0b101)
  59     print ("dmi ctrl status", hex(status))
  60     assert status == 4 # returned old value (nice! cool feature!)
  61
  62     # write DMI address
  63     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
  64
  65     # read DMI CTRL register
  66     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
  67     print ("dmi ctrl status", hex(status))
  68     assert status == 5
  69
  70     # write DMI MSR address
  71     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR)
  72
  73     # read DMI MSR register
  74     msr = yield from jtag_read_write_reg(dut, DMI_READ, 64)
  75     print ("dmi msr", hex(msr))
  76     assert msr == 0xdeadbeef
  77
  78     ####### JTAG to Wishbone ######
  79
  80     # write Wishbone address
  81     yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
  82
  83     # write/read wishbone data
  84     data = yield from jtag_read_write_reg(dut, WB_WRRD, 64, 0xfeef)
  85     print ("wb write", hex(data))
  86
  87     # write Wishbone address
  88     yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
  89
  90     # write/read wishbone data
  91     data = yield from jtag_read_write_reg(dut, WB_READ, 64, 0)
  92     print ("wb read", hex(data))
  93
  94     ####### done - tell dmi_sim to stop (otherwise it won't) ########
  95
  96     srv_dut.stop = True
  97     print ("jtag sim stopping")
  98
  99
 100 if __name__ == '__main__':
 101     dut = JTAG(dummy_pinset(), wb_data_wid=64)
 102     dut.stop = False
 103
 104     # rather than the client access the JTAG bus directly
 105     # create an alternative that the client sets
 106     class Dummy: pass
 107     cdut = Dummy()
 108     cdut.cbus = JTAGInterface()
 109     cdut._ir_width = 4
 110
 111     # set up client-server on port 44843-something
 112     dut.s = JTAGServer()
 113     if len(sys.argv) != 2 or sys.argv[1] != 'server':
 114         cdut.c = JTAGClient()
 115         dut.s.get_connection()
 116     else:
 117         dut.s.get_connection(None) # block waiting for connection
 118
 119     memory = Memory(width=64, depth=16)
 120     sram = SRAM(memory=memory, bus=dut.wb)
 121
 122     m = Module()
 123     m.submodules.ast = dut
 124     m.submodules.sram = sram
 125
 126     sim = Simulator(m)
 127     sim.add_clock(1e-6, domain="sync")      # standard clock
 128
 129     sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server
 130     if len(sys.argv) != 2 or sys.argv[1] != 'server':
 131         sim.add_sync_process(wrap(jtag_sim(cdut, dut))) # actual jtag tester
 132     else:
 133         print ("running server only as requested, use openocd remote to test")
 134     sim.add_sync_process(wrap(dmi_sim(dut)))  # handles (pretends to be) DMI
 135
 136     with sim.write_vcd("dmi2jtag_test_srv.vcd"):
 137         sim.run()