src/soc/debug/test/test_jtag_tap_srv.py

   1 """DMI 2 JTAG test
   2
   3 based on Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 import sys
   7 from nmigen import (Module, Signal, Elaboratable, Const)
   8 from c4m.nmigen.jtag.tap import TAP, IOType
   9 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
  10 from soc.debug.dmi import DMIInterface, DBGCore
  11 from soc.debug.test.dmi_sim import dmi_sim
  12 from soc.debug.jtag import JTAG
  13 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
  14
  15 from soc.bus.sram import SRAM
  16 from nmigen import Memory, Signal, Module
  17
  18 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
  19 from nmutil.util import wrap
  20 from soc.debug.jtagutils import (jtag_read_write_reg,
  21                                  jtag_srv, jtag_set_reset,
  22                                  jtag_set_ir, jtag_set_get_dr)
  23
  24 def test_pinset():
  25     return {
  26             # in, out, tri-out, tri-inout
  27             'test': ['io0-', 'io1+', 'io2>', 'io3*'],
  28            }
  29
  30
  31 # JTAG-ircodes for accessing DMI
  32 DMI_ADDR = 8
  33 DMI_READ = 9
  34 DMI_WRRD = 10
  35
  36 # JTAG-ircodes for accessing Wishbone
  37 WB_ADDR = 5
  38 WB_READ = 6
  39 WB_WRRD = 7
  40
  41 # JTAG boundary scan reg addresses
  42 BS_EXTEST = 0
  43 BS_INTEST = 0
  44 BS_SAMPLE = 2
  45 BS_PRELOAD = 2
  46
  47
  48 def jtag_sim(dut, srv_dut):
  49
  50     ####### JTAGy stuff (IDCODE) ######
  51
  52     # read idcode
  53     yield from jtag_set_reset(dut)
  54     idcode = yield from jtag_read_write_reg(dut, 0b1, 32)
  55     print ("idcode", hex(idcode))
  56     assert idcode == 0x18ff
  57
  58     ####### JTAG Boundary scan ######
  59
  60     bslen = dut.scan_len
  61     print ("scan len", bslen)
  62
  63     # sample test
  64     bs_actual = 0b100110
  65     yield srv_dut.ios[0].pad.i.eq(1)
  66     yield srv_dut.ios[1].core.o.eq(0)
  67     yield srv_dut.ios[2].core.o.eq(1)
  68     yield srv_dut.ios[2].core.oe.eq(1)
  69     yield srv_dut.ios[3].pad.i.eq(0)
  70     yield srv_dut.ios[3].core.o.eq(0)
  71     yield srv_dut.ios[3].core.oe.eq(1)
  72     yield
  73
  74     bs = yield from jtag_read_write_reg(dut, BS_SAMPLE, bslen, bs_actual)
  75     print ("bs scan", bin(bs))
  76     yield
  77
  78     print ("io0 pad.i", (yield srv_dut.ios[0].core.i))
  79     print ("io1 core.o", (yield srv_dut.ios[1].pad.o))
  80     print ("io2 core.o", (yield srv_dut.ios[2].pad.o))
  81     print ("io2 core.oe", (yield srv_dut.ios[2].pad.oe))
  82     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
  83     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
  84     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
  85
  86     assert (yield srv_dut.ios[0].core.i) == 1
  87     assert (yield srv_dut.ios[1].pad.o) == 0
  88     assert (yield srv_dut.ios[2].pad.o) == 1
  89     assert (yield srv_dut.ios[2].pad.oe) == 1
  90     assert (yield srv_dut.ios[3].core.i) == 0
  91     assert (yield srv_dut.ios[3].pad.o) == 0
  92     assert (yield srv_dut.ios[3].pad.oe) == 1
  93
  94     # extest
  95     ir_actual = yield from jtag_set_ir(dut, BS_EXTEST)
  96     print ("ir extest", bin(ir_actual))
  97     yield
  98
  99     print ("io0 pad.i", (yield srv_dut.ios[0].core.i))
 100     print ("io1 core.o", (yield srv_dut.ios[1].pad.o))
 101     print ("io2 core.o", (yield srv_dut.ios[2].pad.o))
 102     print ("io2 core.oe", (yield srv_dut.ios[2].pad.oe))
 103     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
 104     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
 105     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
 106
 107     assert (yield srv_dut.ios[0].core.i) == 0
 108     assert (yield srv_dut.ios[1].pad.o) == 1
 109     assert (yield srv_dut.ios[2].pad.o) == 0
 110     assert (yield srv_dut.ios[2].pad.oe) == 0
 111     assert (yield srv_dut.ios[3].core.i) == 1
 112     assert (yield srv_dut.ios[3].pad.o) == 1
 113     assert (yield srv_dut.ios[3].pad.oe) == 0
 114
 115     # set pins
 116     bs_actual = 0b1011001
 117     yield srv_dut.ios[0].pad.i.eq(0)
 118     yield srv_dut.ios[1].core.o.eq(1)
 119     yield srv_dut.ios[2].core.o.eq(0)
 120     yield srv_dut.ios[2].core.oe.eq(0)
 121     yield srv_dut.ios[3].pad.i.eq(1)
 122     yield srv_dut.ios[3].core.o.eq(1)
 123     yield srv_dut.ios[3].core.oe.eq(0)
 124     yield
 125
 126     bs = yield from jtag_set_get_dr(dut, bslen, bs_actual)
 127     print ("bs scan", bin(bs))
 128     yield
 129
 130     print ("io0 pad.i", (yield srv_dut.ios[0].core.i))
 131     print ("io1 core.o", (yield srv_dut.ios[1].pad.o))
 132     print ("io2 core.o", (yield srv_dut.ios[2].pad.o))
 133     print ("io2 core.oe", (yield srv_dut.ios[2].pad.oe))
 134     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
 135     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
 136     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
 137
 138     assert (yield srv_dut.ios[0].core.i) == 1
 139     assert (yield srv_dut.ios[1].pad.o) == 0
 140     assert (yield srv_dut.ios[2].pad.o) == 1
 141     assert (yield srv_dut.ios[2].pad.oe) == 1
 142     assert (yield srv_dut.ios[3].core.i) == 0
 143     assert (yield srv_dut.ios[3].pad.o) == 0
 144     assert (yield srv_dut.ios[3].pad.oe) == 1
 145
 146     # reset
 147     yield from jtag_set_reset(dut)
 148     print ("bs reset")
 149     yield
 150
 151     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
 152     print ("io1 core.o", (yield srv_dut.ios[1].core.o))
 153     print ("io2 core.o", (yield srv_dut.ios[2].core.o))
 154     print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
 155     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
 156     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
 157     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
 158
 159     assert (yield srv_dut.ios[0].core.i) == 0
 160     assert (yield srv_dut.ios[1].pad.o) == 1
 161     assert (yield srv_dut.ios[2].pad.o) == 0
 162     assert (yield srv_dut.ios[2].pad.oe) == 0
 163     assert (yield srv_dut.ios[3].core.i) == 1
 164     assert (yield srv_dut.ios[3].pad.o) == 1
 165     assert (yield srv_dut.ios[3].pad.oe) == 0
 166
 167     ####### JTAG to DMI ######
 168
 169     # write DMI address
 170     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
 171
 172     # read DMI CTRL register
 173     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
 174     print ("dmi ctrl status", hex(status))
 175     assert status == 4
 176
 177     # write DMI address
 178     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, 0)
 179
 180     # write DMI CTRL register
 181     status = yield from jtag_read_write_reg(dut, DMI_WRRD, 64, 0b101)
 182     print ("dmi ctrl status", hex(status))
 183     assert status == 4 # returned old value (nice! cool feature!)
 184
 185     # write DMI address
 186     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
 187
 188     # read DMI CTRL register
 189     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
 190     print ("dmi ctrl status", hex(status))
 191     assert status == 6
 192
 193     # write DMI MSR address
 194     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR)
 195
 196     # read DMI MSR register
 197     msr = yield from jtag_read_write_reg(dut, DMI_READ, 64)
 198     print ("dmi msr", hex(msr))
 199     assert msr == 0xdeadbeef
 200
 201     ####### JTAG to Wishbone ######
 202
 203     # write Wishbone address
 204     yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
 205
 206     # write/read wishbone data
 207     data = yield from jtag_read_write_reg(dut, WB_WRRD, 64, 0xfeef)
 208     print ("wb write", hex(data))
 209
 210     # write Wishbone address
 211     yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
 212
 213     # write/read wishbone data
 214     data = yield from jtag_read_write_reg(dut, WB_READ, 64, 0)
 215     print ("wb read", hex(data))
 216
 217     ####### done - tell dmi_sim to stop (otherwise it won't) ########
 218
 219     srv_dut.stop = True
 220     print ("jtag sim stopping")
 221
 222
 223 if __name__ == '__main__':
 224     dut = JTAG(test_pinset(), wb_data_wid=64, domain="sync")
 225     dut.stop = False
 226
 227     # rather than the client access the JTAG bus directly
 228     # create an alternative that the client sets
 229     class Dummy: pass
 230     cdut = Dummy()
 231     cdut.cbus = JTAGInterface()
 232
 233     # set up client-server on port 44843-something
 234     dut.s = JTAGServer()
 235     if len(sys.argv) != 2 or sys.argv[1] != 'server':
 236         cdut.c = JTAGClient()
 237         dut.s.get_connection()
 238     else:
 239         print ("running server only as requested, use openocd remote to test")
 240         sys.stdout.flush()
 241         dut.s.get_connection(None) # block waiting for connection
 242
 243     # take copy of ir_width and scan_len
 244     cdut._ir_width = dut._ir_width
 245     cdut.scan_len = dut.scan_len
 246
 247     memory = Memory(width=64, depth=16)
 248     sram = SRAM(memory=memory, bus=dut.wb)
 249
 250     m = Module()
 251     m.submodules.ast = dut
 252     m.submodules.sram = sram
 253
 254     sim = Simulator(m)
 255     sim.add_clock(1e-6, domain="sync")      # standard clock
 256
 257     sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server
 258     if len(sys.argv) != 2 or sys.argv[1] != 'server':
 259         sim.add_sync_process(wrap(jtag_sim(cdut, dut))) # actual jtag tester
 260     sim.add_sync_process(wrap(dmi_sim(dut)))  # handles (pretends to be) DMI
 261
 262     with sim.write_vcd("dmi2jtag_test_srv.vcd"):
 263         sim.run()