7f3709095dccb340c065888ec204a583ec0dd9c1
1 """Decode2ToExecute1Type
3 based on Anton Blanchard microwatt decode2.vhdl
6 from nmigen
import Signal
, Record
7 from nmutil
.iocontrol
import RecordObject
8 from soc
.decoder
.power_enums
import InternalOp
, CryIn
, Function
13 def __init__(self
, width
, name
):
14 name_ok
= "%s_ok" % name
15 layout
= ((name
, width
), (name_ok
, 1))
16 Record
.__init
__(self
, layout
)
17 self
.data
= getattr(self
, name
) # convenience
18 self
.ok
= getattr(self
, name_ok
) # convenience
19 self
.data
.reset_less
= True # grrr
20 self
.reset_less
= True # grrr
23 return [self
.data
, self
.ok
]
26 class Decode2ToExecute1Type(RecordObject
):
28 def __init__(self
, name
=None):
30 RecordObject
.__init
__(self
, name
=name
)
32 self
.valid
= Signal(reset_less
=True)
33 self
.insn_type
= Signal(InternalOp
, reset_less
=True)
34 self
.fn_unit
= Signal(Function
, reset_less
=True)
35 self
.nia
= Signal(64, reset_less
=True)
36 self
.write_reg
= Data(5, name
="rego")
37 self
.write_ea
= Data(5, name
="ea") # for LD/ST in update mode
38 self
.read_reg1
= Data(5, name
="reg1")
39 self
.read_reg2
= Data(5, name
="reg2")
40 self
.read_reg3
= Data(5, name
="reg3")
41 self
.imm_data
= Data(64, name
="imm")
42 self
.write_spr
= Data(10, name
="spro")
43 self
.read_spr1
= Data(10, name
="spr1")
44 self
.read_spr2
= Data(10, name
="spr2")
46 self
.read_fast1
= Data(3, name
="fast1")
47 self
.read_fast2
= Data(3, name
="fast2")
48 self
.write_fast1
= Data(3, name
="fasto1")
49 self
.write_fast2
= Data(3, name
="fasto2")
51 self
.read_cr1
= Data(3, name
="cr_in1")
52 self
.read_cr2
= Data(3, name
="cr_in2")
53 self
.read_cr3
= Data(3, name
="cr_in2")
54 self
.read_cr_whole
= Signal(reset_less
=True)
55 self
.write_cr
= Data(3, name
="cr_out")
56 self
.write_cr_whole
= Signal(reset_less
=True)
57 self
.lk
= Signal(reset_less
=True)
58 self
.rc
= Data(1, "rc")
59 self
.oe
= Data(1, "oe")
60 self
.invert_a
= Signal(reset_less
=True)
61 self
.zero_a
= Signal(reset_less
=True)
62 self
.invert_out
= Signal(reset_less
=True)
63 self
.input_carry
= Signal(CryIn
, reset_less
=True)
64 self
.output_carry
= Signal(reset_less
=True)
65 self
.input_cr
= Signal(reset_less
=True) # instr. has a CR as input
66 self
.output_cr
= Signal(reset_less
=True) # instr. has a CR as output
67 self
.is_32bit
= Signal(reset_less
=True)
68 self
.is_signed
= Signal(reset_less
=True)
69 self
.insn
= Signal(32, reset_less
=True)
70 self
.data_len
= Signal(4, reset_less
=True) # bytes
71 self
.byte_reverse
= Signal(reset_less
=True)
72 self
.sign_extend
= Signal(reset_less
=True)# do we need this?
73 self
.update
= Signal(reset_less
=True) # LD/ST is "update" variant
74 self
.traptype
= Signal(4, reset_less
=True) # see trap main_stage.py
75 self
.trapaddr
= Signal(13, reset_less
=True)