src/soc/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
   9 from soc.consts import TT
  10 from soc.experiment.mem_types import LDSTException
  11
  12
  13 class Data(Record):
  14
  15     def __init__(self, width, name):
  16         name_ok = "%s_ok" % name
  17         layout = ((name, width), (name_ok, 1))
  18         Record.__init__(self, layout)
  19         self.data = getattr(self, name) # convenience
  20         self.ok = getattr(self, name_ok) # convenience
  21         self.data.reset_less = True # grrr
  22         self.reset_less = True # grrr
  23
  24     def ports(self):
  25         return [self.data, self.ok]
  26
  27
  28 class IssuerDecode2ToOperand(RecordObject):
  29     """IssuerDecode2ToOperand
  30
  31     contains the subset of fields needed for Issuer to decode the instruction
  32     and get register rdflags signals set up.  it also doubles up as the
  33     "Trap" temporary store, because part of the Decoder's job is to
  34     identify whether a trap / interrupt / exception should occur.
  35     """
  36
  37     def __init__(self, name=None):
  38
  39         RecordObject.__init__(self, name=name)
  40
  41         # current "state" (TODO: this in its own Record)
  42         self.msr = Signal(64, reset_less=True)
  43         self.cia = Signal(64, reset_less=True)
  44
  45         # instruction, type and decoded information
  46         self.insn = Signal(32, reset_less=True) # original instruction
  47         self.insn_type = Signal(MicrOp, reset_less=True)
  48         self.fn_unit = Signal(Function, reset_less=True)
  49         self.lk = Signal(reset_less=True)
  50         self.rc = Data(1, "rc")
  51         self.oe = Data(1, "oe")
  52         self.input_carry = Signal(CryIn, reset_less=True)
  53         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
  54         self.ldst_exc  = LDSTException("exc")
  55         self.trapaddr  = Signal(13, reset_less=True)
  56         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
  57         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
  58         self.is_32bit = Signal(reset_less=True)
  59
  60
  61 class Decode2ToOperand(IssuerDecode2ToOperand):
  62
  63     def __init__(self, name=None):
  64
  65         IssuerDecode2ToOperand.__init__(self, name=name)
  66
  67         # instruction, type and decoded information
  68         self.imm_data = Data(64, name="imm")
  69         self.invert_in = Signal(reset_less=True)
  70         self.zero_a = Signal(reset_less=True)
  71         self.output_carry = Signal(reset_less=True)
  72         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
  73         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
  74         self.invert_out = Signal(reset_less=True)
  75         self.is_32bit = Signal(reset_less=True)
  76         self.is_signed = Signal(reset_less=True)
  77         self.data_len = Signal(4, reset_less=True) # bytes
  78         self.byte_reverse  = Signal(reset_less=True)
  79         self.sign_extend  = Signal(reset_less=True)# do we need this?
  80         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
  81         self.write_cr0 = Signal(reset_less=True)
  82
  83
  84 class Decode2ToExecute1Type(RecordObject):
  85
  86     def __init__(self, name=None, asmcode=True, opkls=None, do=None):
  87
  88         if do is None and opkls is None:
  89             opkls = Decode2ToOperand
  90
  91         RecordObject.__init__(self, name=name)
  92
  93         if asmcode:
  94             self.asmcode = Signal(8, reset_less=True) # only for simulator
  95         self.write_reg = Data(7, name="rego")
  96         self.write_ea = Data(7, name="ea") # for LD/ST in update mode
  97         self.read_reg1 = Data(7, name="reg1")
  98         self.read_reg2 = Data(7, name="reg2")
  99         self.read_reg3 = Data(7, name="reg3")
 100         self.write_spr = Data(SPR, name="spro")
 101         self.read_spr1 = Data(SPR, name="spr1")
 102         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 103
 104         self.xer_in = Signal(3, reset_less=True)   # xer might be read
 105         self.xer_out = Signal(reset_less=True)  # xer might be written
 106
 107         self.read_fast1 = Data(3, name="fast1")
 108         self.read_fast2 = Data(3, name="fast2")
 109         self.write_fast1 = Data(3, name="fasto1")
 110         self.write_fast2 = Data(3, name="fasto2")
 111
 112         self.read_cr1 = Data(7, name="cr_in1")
 113         self.read_cr2 = Data(7, name="cr_in2")
 114         self.read_cr3 = Data(7, name="cr_in2")
 115         self.write_cr = Data(7, name="cr_out")
 116
 117         # decode operand data
 118         print ("decode2execute init", name, opkls, do)
 119         #assert name is not None, str(opkls)
 120         if do is not None:
 121             self.do = do
 122         else:
 123             self.do = opkls(name)