src/soc/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
   9 from soc.consts import TT
  10
  11
  12 class Data(Record):
  13
  14     def __init__(self, width, name):
  15         name_ok = "%s_ok" % name
  16         layout = ((name, width), (name_ok, 1))
  17         Record.__init__(self, layout)
  18         self.data = getattr(self, name) # convenience
  19         self.ok = getattr(self, name_ok) # convenience
  20         self.data.reset_less = True # grrr
  21         self.reset_less = True # grrr
  22
  23     def ports(self):
  24         return [self.data, self.ok]
  25
  26
  27 class IssuerDecode2ToOperand(RecordObject):
  28     """IssuerDecode2ToOperand
  29
  30     contains the subset of fields needed for Issuer to decode the instruction
  31     and get register rdflags signals set up.  it also doubles up as the
  32     "Trap" temporary store, because part of the Decoder's job is to
  33     identify whether a trap / interrupt / exception should occur.
  34     """
  35
  36     def __init__(self, name=None):
  37
  38         RecordObject.__init__(self, name=name)
  39
  40         # current "state" (TODO: this in its own Record)
  41         self.msr = Signal(64, reset_less=True)
  42         self.cia = Signal(64, reset_less=True)
  43
  44         # instruction, type and decoded information
  45         self.insn = Signal(32, reset_less=True) # original instruction
  46         self.insn_type = Signal(MicrOp, reset_less=True)
  47         self.fn_unit = Signal(Function, reset_less=True)
  48         self.lk = Signal(reset_less=True)
  49         self.rc = Data(1, "rc")
  50         self.oe = Data(1, "oe")
  51         self.input_carry = Signal(CryIn, reset_less=True)
  52         self.traptype  = Signal(TT.size, reset_less=True) # trap main_stage.py
  53         self.trapaddr  = Signal(13, reset_less=True)
  54         self.read_cr_whole = Data(8, "cr_rd") # CR full read mask
  55         self.write_cr_whole = Data(8, "cr_wr") # CR full write mask
  56         self.is_32bit = Signal(reset_less=True)
  57
  58
  59 class Decode2ToOperand(IssuerDecode2ToOperand):
  60
  61     def __init__(self, name=None):
  62
  63         IssuerDecode2ToOperand.__init__(self, name=name)
  64
  65         # instruction, type and decoded information
  66         self.imm_data = Data(64, name="imm")
  67         self.invert_in = Signal(reset_less=True)
  68         self.zero_a = Signal(reset_less=True)
  69         self.output_carry = Signal(reset_less=True)
  70         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
  71         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
  72         self.invert_out = Signal(reset_less=True)
  73         self.is_32bit = Signal(reset_less=True)
  74         self.is_signed = Signal(reset_less=True)
  75         self.data_len = Signal(4, reset_less=True) # bytes
  76         self.byte_reverse  = Signal(reset_less=True)
  77         self.sign_extend  = Signal(reset_less=True)# do we need this?
  78         self.ldst_mode  = Signal(LDSTMode, reset_less=True) # LD/ST mode
  79         self.write_cr0 = Signal(reset_less=True)
  80
  81
  82 class Decode2ToExecute1Type(RecordObject):
  83
  84     def __init__(self, name=None, asmcode=True, opkls=None):
  85
  86         if opkls is None:
  87             opkls = Decode2ToOperand
  88
  89         RecordObject.__init__(self, name=name)
  90
  91         if asmcode:
  92             self.asmcode = Signal(8, reset_less=True) # only for simulator
  93         self.write_reg = Data(5, name="rego")
  94         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
  95         self.read_reg1 = Data(5, name="reg1")
  96         self.read_reg2 = Data(5, name="reg2")
  97         self.read_reg3 = Data(5, name="reg3")
  98         self.write_spr = Data(SPR, name="spro")
  99         self.read_spr1 = Data(SPR, name="spr1")
 100         #self.read_spr2 = Data(SPR, name="spr2") # only one needed
 101
 102         self.xer_in = Signal(3, reset_less=True)   # xer might be read
 103         self.xer_out = Signal(reset_less=True)  # xer might be written
 104
 105         self.read_fast1 = Data(3, name="fast1")
 106         self.read_fast2 = Data(3, name="fast2")
 107         self.write_fast1 = Data(3, name="fasto1")
 108         self.write_fast2 = Data(3, name="fasto2")
 109
 110         self.read_cr1 = Data(3, name="cr_in1")
 111         self.read_cr2 = Data(3, name="cr_in2")
 112         self.read_cr3 = Data(3, name="cr_in2")
 113         self.write_cr = Data(3, name="cr_out")
 114
 115         # decode operand data
 116         print ("decode2execute init", name, opkls)
 117         #assert name is not None, str(opkls)
 118         self.do = opkls(name)