add PC (CIA) to PowerDecode2 "state" for passing into input records
[soc.git] / src / soc / decoder / decode2execute1.py
1 """Decode2ToExecute1Type
2
3 based on Anton Blanchard microwatt decode2.vhdl
4
5 """
6 from nmigen import Signal, Record
7 from nmutil.iocontrol import RecordObject
8 from soc.decoder.power_enums import MicrOp, CryIn, Function, SPR, LDSTMode
9
10
11 class Data(Record):
12
13 def __init__(self, width, name):
14 name_ok = "%s_ok" % name
15 layout = ((name, width), (name_ok, 1))
16 Record.__init__(self, layout)
17 self.data = getattr(self, name) # convenience
18 self.ok = getattr(self, name_ok) # convenience
19 self.data.reset_less = True # grrr
20 self.reset_less = True # grrr
21
22 def ports(self):
23 return [self.data, self.ok]
24
25
26 class Decode2ToOperand(RecordObject):
27
28 def __init__(self, name=None):
29
30 RecordObject.__init__(self, name=name)
31
32 # current "state" (TODO: this in its own Record)
33 self.msr = Signal(64, reset_less=True)
34 self.cia = Signal(64, reset_less=True)
35
36 # instruction, type and decoded information
37 self.insn = Signal(32, reset_less=True) # original instruction
38 self.insn_type = Signal(MicrOp, reset_less=True)
39 self.fn_unit = Signal(Function, reset_less=True)
40 self.imm_data = Data(64, name="imm")
41 self.lk = Signal(reset_less=True)
42 self.rc = Data(1, "rc")
43 self.oe = Data(1, "oe")
44 self.invert_a = Signal(reset_less=True)
45 self.zero_a = Signal(reset_less=True)
46 self.input_carry = Signal(CryIn, reset_less=True)
47 self.output_carry = Signal(reset_less=True)
48 self.input_cr = Signal(reset_less=True) # instr. has a CR as input
49 self.output_cr = Signal(reset_less=True) # instr. has a CR as output
50 self.invert_out = Signal(reset_less=True)
51 self.is_32bit = Signal(reset_less=True)
52 self.is_signed = Signal(reset_less=True)
53 self.data_len = Signal(4, reset_less=True) # bytes
54 self.byte_reverse = Signal(reset_less=True)
55 self.sign_extend = Signal(reset_less=True)# do we need this?
56 self.ldst_mode = Signal(LDSTMode, reset_less=True) # LD/ST mode
57 self.traptype = Signal(5, reset_less=True) # see trap main_stage.py
58 self.trapaddr = Signal(13, reset_less=True)
59 self.read_cr_whole = Signal(reset_less=True)
60 self.write_cr_whole = Signal(reset_less=True)
61 self.write_cr0 = Signal(reset_less=True)
62
63
64 class Decode2ToExecute1Type(RecordObject):
65
66 def __init__(self, name=None, asmcode=True):
67
68 RecordObject.__init__(self, name=name)
69
70 if asmcode:
71 self.asmcode = Signal(8, reset_less=True) # only for simulator
72 self.write_reg = Data(5, name="rego")
73 self.write_ea = Data(5, name="ea") # for LD/ST in update mode
74 self.read_reg1 = Data(5, name="reg1")
75 self.read_reg2 = Data(5, name="reg2")
76 self.read_reg3 = Data(5, name="reg3")
77 self.write_spr = Data(SPR, name="spro")
78 self.read_spr1 = Data(SPR, name="spr1")
79 #self.read_spr2 = Data(SPR, name="spr2") # only one needed
80
81 self.xer_in = Signal(reset_less=True) # xer might be read
82 self.xer_out = Signal(reset_less=True) # xer might be written
83
84 self.read_fast1 = Data(3, name="fast1")
85 self.read_fast2 = Data(3, name="fast2")
86 self.write_fast1 = Data(3, name="fasto1")
87 self.write_fast2 = Data(3, name="fasto2")
88
89 self.read_cr1 = Data(3, name="cr_in1")
90 self.read_cr2 = Data(3, name="cr_in2")
91 self.read_cr3 = Data(3, name="cr_in2")
92 self.write_cr = Data(3, name="cr_out")
93
94 # decode operand data
95 self.do = Decode2ToOperand(name)