src/soc/decoder/decode2execute1.py

   1 """Decode2ToExecute1Type
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 """
   6 from nmigen import Signal, Record
   7 from nmutil.iocontrol import RecordObject
   8 from soc.decoder.power_enums import InternalOp, CryIn, Function, SPR
   9
  10
  11 class Data(Record):
  12
  13     def __init__(self, width, name):
  14         name_ok = "%s_ok" % name
  15         layout = ((name, width), (name_ok, 1))
  16         Record.__init__(self, layout)
  17         self.data = getattr(self, name) # convenience
  18         self.ok = getattr(self, name_ok) # convenience
  19         self.data.reset_less = True # grrr
  20         self.reset_less = True # grrr
  21
  22     def ports(self):
  23         return [self.data, self.ok]
  24
  25
  26 class Decode2ToExecute1Type(RecordObject):
  27
  28     def __init__(self, name=None, asmcode=True):
  29
  30         RecordObject.__init__(self, name=name)
  31
  32         self.valid = Signal(reset_less=True)
  33         self.insn_type = Signal(InternalOp, reset_less=True)
  34         self.fn_unit = Signal(Function, reset_less=True)
  35         if asmcode:
  36             self.asmcode = Signal(8, reset_less=True) # only for simulator
  37         self.nia = Signal(64, reset_less=True)
  38         self.write_reg = Data(5, name="rego")
  39         self.write_ea = Data(5, name="ea") # for LD/ST in update mode
  40         self.read_reg1 = Data(5, name="reg1")
  41         self.read_reg2 = Data(5, name="reg2")
  42         self.read_reg3 = Data(5, name="reg3")
  43         self.imm_data = Data(64, name="imm")
  44         self.write_spr = Data(SPR, name="spro")
  45         self.read_spr1 = Data(SPR, name="spr1")
  46         #self.read_spr2 = Data(SPR, name="spr2")
  47
  48         self.read_fast1 = Data(3, name="fast1")
  49         self.read_fast2 = Data(3, name="fast2")
  50         self.write_fast1 = Data(3, name="fasto1")
  51         self.write_fast2 = Data(3, name="fasto2")
  52
  53         self.read_cr1 = Data(3, name="cr_in1")
  54         self.read_cr2 = Data(3, name="cr_in2")
  55         self.read_cr3 = Data(3, name="cr_in2")
  56         self.read_cr_whole = Signal(reset_less=True)
  57         self.write_cr = Data(3, name="cr_out")
  58         self.write_cr_whole = Signal(reset_less=True)
  59         self.lk = Signal(reset_less=True)
  60         self.rc = Data(1, "rc")
  61         self.oe = Data(1, "oe")
  62         self.invert_a = Signal(reset_less=True)
  63         self.zero_a = Signal(reset_less=True)
  64         self.invert_out = Signal(reset_less=True)
  65         self.input_carry = Signal(CryIn, reset_less=True)
  66         self.output_carry = Signal(reset_less=True)
  67         self.input_cr = Signal(reset_less=True)  # instr. has a CR as input
  68         self.output_cr = Signal(reset_less=True) # instr. has a CR as output
  69         self.is_32bit = Signal(reset_less=True)
  70         self.is_signed = Signal(reset_less=True)
  71         self.insn = Signal(32, reset_less=True)
  72         self.data_len = Signal(4, reset_less=True) # bytes
  73         self.byte_reverse  = Signal(reset_less=True)
  74         self.sign_extend  = Signal(reset_less=True)# do we need this?
  75         self.update  = Signal(reset_less=True) # LD/ST is "update" variant
  76         self.traptype  = Signal(5, reset_less=True) # see trap main_stage.py
  77         self.trapaddr  = Signal(13, reset_less=True)
  78