src/soc/decoder/isa/caller.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020 Michael Nolan
   4 # Funded by NLnet http://nlnet.nl
   5 """core of the python-based POWER9 simulator
   6
   7 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   8 not speed, it is for both learning and educational purposes, as well as
   9 a method of verifying the HDL.
  10
  11 related bugs:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
  14 """
  15
  16 from nmigen.back.pysim import Settle
  17 from functools import wraps
  18 from copy import copy
  19 from soc.decoder.orderedset import OrderedSet
  20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  21                                         selectconcat)
  22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
  23                                      insns, MicrOp, In1Sel, In2Sel, In3Sel,
  24                                      OutSel, CROutSel,
  25                                      SVP64RMMode, SVP64PredMode,
  26                                      SVP64PredInt, SVP64PredCR)
  27
  28 from soc.decoder.power_enums import SVPtype
  29
  30 from soc.decoder.helpers import exts, gtu, ltu, undefined
  31 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
  32 from soc.consts import SVP64CROffs
  33 from soc.decoder.power_svp64 import SVP64RM, decode_extra
  34
  35 from soc.decoder.isa.radixmmu import RADIX
  36 from soc.decoder.isa.mem import Mem, swap_order
  37
  38 from collections import namedtuple
  39 import math
  40 import sys
  41
  42 instruction_info = namedtuple('instruction_info',
  43                               'func read_regs uninit_regs write_regs ' +
  44                               'special_regs op_fields form asmregs')
  45
  46 special_sprs = {
  47     'LR': 8,
  48     'CTR': 9,
  49     'TAR': 815,
  50     'XER': 1,
  51     'VRSAVE': 256}
  52
  53
  54 REG_SORT_ORDER = {
  55     # TODO (lkcl): adjust other registers that should be in a particular order
  56     # probably CA, CA32, and CR
  57     "RT": 0,
  58     "RA": 0,
  59     "RB": 0,
  60     "RS": 0,
  61     "CR": 0,
  62     "LR": 0,
  63     "CTR": 0,
  64     "TAR": 0,
  65     "CA": 0,
  66     "CA32": 0,
  67     "MSR": 0,
  68     "SVSTATE": 0,
  69
  70     "overflow": 1,
  71 }
  72
  73
  74 def create_args(reglist, extra=None):
  75     retval = list(OrderedSet(reglist))
  76     retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
  77     if extra is not None:
  78         return [extra] + retval
  79     return retval
  80
  81
  82
  83 class GPR(dict):
  84     def __init__(self, decoder, isacaller, svstate, regfile):
  85         dict.__init__(self)
  86         self.sd = decoder
  87         self.isacaller = isacaller
  88         self.svstate = svstate
  89         for i in range(32):
  90             self[i] = SelectableInt(regfile[i], 64)
  91
  92     def __call__(self, ridx):
  93         return self[ridx]
  94
  95     def set_form(self, form):
  96         self.form = form
  97
  98     def getz(self, rnum):
  99         # rnum = rnum.value # only SelectableInt allowed
 100         print("GPR getzero?", rnum)
 101         if rnum == 0:
 102             return SelectableInt(0, 64)
 103         return self[rnum]
 104
 105     def _get_regnum(self, attr):
 106         getform = self.sd.sigforms[self.form]
 107         rnum = getattr(getform, attr)
 108         return rnum
 109
 110     def ___getitem__(self, attr):
 111         """ XXX currently not used
 112         """
 113         rnum = self._get_regnum(attr)
 114         offs = self.svstate.srcstep
 115         print("GPR getitem", attr, rnum, "srcoffs", offs)
 116         return self.regfile[rnum]
 117
 118     def dump(self):
 119         for i in range(0, len(self), 8):
 120             s = []
 121             for j in range(8):
 122                 s.append("%08x" % self[i+j].value)
 123             s = ' '.join(s)
 124             print("reg", "%2d" % i, s)
 125
 126
 127 class PC:
 128     def __init__(self, pc_init=0):
 129         self.CIA = SelectableInt(pc_init, 64)
 130         self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
 131
 132     def update_nia(self, is_svp64):
 133         increment = 8 if is_svp64 else 4
 134         self.NIA = self.CIA + SelectableInt(increment, 64)
 135
 136     def update(self, namespace, is_svp64):
 137         """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
 138         """
 139         self.CIA = namespace['NIA'].narrow(64)
 140         self.update_nia(is_svp64)
 141         namespace['CIA'] = self.CIA
 142         namespace['NIA'] = self.NIA
 143
 144
 145 # Simple-V: see https://libre-soc.org/openpower/sv
 146 class SVP64State:
 147     def __init__(self, init=0):
 148         self.spr = SelectableInt(init, 32)
 149         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
 150         self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
 151         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
 152         self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
 153         self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
 154         self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
 155         self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
 156
 157
 158 # SVP64 ReMap field
 159 class SVP64RMFields:
 160     def __init__(self, init=0):
 161         self.spr = SelectableInt(init, 24)
 162         # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
 163         self.mmode = FieldSelectableInt(self.spr, [0])
 164         self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
 165         self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
 166         self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
 167         self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
 168         self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
 169         self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
 170         # these cover the same extra field, split into parts as EXTRA2
 171         self.extra2 = list(range(4))
 172         self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
 173         self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
 174         self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
 175         self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
 176         self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
 177         # and here as well, but EXTRA3
 178         self.extra3 = list(range(3))
 179         self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
 180         self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
 181         self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
 182
 183
 184 SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)
 185 SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)
 186 SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)
 187 SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)
 188 SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)
 189 SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)
 190 SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)
 191 SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)
 192 SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)
 193
 194
 195 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
 196 class SVP64PrefixFields:
 197     def __init__(self):
 198         self.insn = SelectableInt(0, 32)
 199         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
 200         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
 201         self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
 202         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
 203         self.rm = FieldSelectableInt(self.insn, rmfields)
 204
 205
 206 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
 207 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
 208 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
 209
 210 # decode SVP64 predicate integer to reg number and invert
 211 def get_predint(gpr, mask):
 212     r10 = gpr(10)
 213     r30 = gpr(30)
 214     if mask == SVP64PredInt.ALWAYS.value:
 215         return 0xffff_ffff_ffff_ffff
 216     if mask == SVP64PredInt.R3_UNARY.value:
 217         return 1 << (gpr(3).value & 0b111111)
 218     if mask == SVP64PredInt.R3.value:
 219         return gpr(3).value
 220     if mask == SVP64PredInt.R3_N.value:
 221         return ~gpr(3).value
 222     if mask == SVP64PredInt.R10.value:
 223         return gpr(10).value
 224     if mask == SVP64PredInt.R10_N.value:
 225         return ~gpr(10).value
 226     if mask == SVP64PredInt.R30.value:
 227         return gpr(30).value
 228     if mask == SVP64PredInt.R30_N.value:
 229         return ~gpr(30).value
 230
 231 # decode SVP64 predicate CR to reg number and invert
 232 def _get_predcr(mask):
 233     if mask == SVP64PredCR.LT.value:
 234         return 0, 1
 235     if mask == SVP64PredCR.GE.value:
 236         return 0, 0
 237     if mask == SVP64PredCR.GT.value:
 238         return 1, 1
 239     if mask == SVP64PredCR.LE.value:
 240         return 1, 0
 241     if mask == SVP64PredCR.EQ.value:
 242         return 2, 1
 243     if mask == SVP64PredCR.NE.value:
 244         return 2, 0
 245     if mask == SVP64PredCR.SO.value:
 246         return 3, 1
 247     if mask == SVP64PredCR.NS.value:
 248         return 3, 0
 249
 250 def get_predcr(crl, mask, vl):
 251     idx, noninv = _get_predcr(mask)
 252     mask = 0
 253     for i in range(vl):
 254         cr = crl[i+SVP64CROffs.CRPred]
 255         if cr[idx].value == noninv:
 256             mask |= (1<<i)
 257     return mask
 258
 259
 260 class SPR(dict):
 261     def __init__(self, dec2, initial_sprs={}):
 262         self.sd = dec2
 263         dict.__init__(self)
 264         for key, v in initial_sprs.items():
 265             if isinstance(key, SelectableInt):
 266                 key = key.value
 267             key = special_sprs.get(key, key)
 268             if isinstance(key, int):
 269                 info = spr_dict[key]
 270             else:
 271                 info = spr_byname[key]
 272             if not isinstance(v, SelectableInt):
 273                 v = SelectableInt(v, info.length)
 274             self[key] = v
 275
 276     def __getitem__(self, key):
 277         print("get spr", key)
 278         print("dict", self.items())
 279         # if key in special_sprs get the special spr, otherwise return key
 280         if isinstance(key, SelectableInt):
 281             key = key.value
 282         if isinstance(key, int):
 283             key = spr_dict[key].SPR
 284         key = special_sprs.get(key, key)
 285         if key == 'HSRR0':  # HACK!
 286             key = 'SRR0'
 287         if key == 'HSRR1':  # HACK!
 288             key = 'SRR1'
 289         if key in self:
 290             res = dict.__getitem__(self, key)
 291         else:
 292             if isinstance(key, int):
 293                 info = spr_dict[key]
 294             else:
 295                 info = spr_byname[key]
 296             dict.__setitem__(self, key, SelectableInt(0, info.length))
 297             res = dict.__getitem__(self, key)
 298         print("spr returning", key, res)
 299         return res
 300
 301     def __setitem__(self, key, value):
 302         if isinstance(key, SelectableInt):
 303             key = key.value
 304         if isinstance(key, int):
 305             key = spr_dict[key].SPR
 306             print("spr key", key)
 307         key = special_sprs.get(key, key)
 308         if key == 'HSRR0':  # HACK!
 309             self.__setitem__('SRR0', value)
 310         if key == 'HSRR1':  # HACK!
 311             self.__setitem__('SRR1', value)
 312         print("setting spr", key, value)
 313         dict.__setitem__(self, key, value)
 314
 315     def __call__(self, ridx):
 316         return self[ridx]
 317
 318 def get_pdecode_idx_in(dec2, name):
 319     op = dec2.dec.op
 320     in1_sel = yield op.in1_sel
 321     in2_sel = yield op.in2_sel
 322     in3_sel = yield op.in3_sel
 323     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 324     in1 = yield dec2.e.read_reg1.data
 325     in2 = yield dec2.e.read_reg2.data
 326     in3 = yield dec2.e.read_reg3.data
 327     in1_isvec = yield dec2.in1_isvec
 328     in2_isvec = yield dec2.in2_isvec
 329     in3_isvec = yield dec2.in3_isvec
 330     print ("get_pdecode_idx_in in1", name, in1_sel, In1Sel.RA.value,
 331                                      in1, in1_isvec)
 332     print ("get_pdecode_idx_in in2", name, in2_sel, In2Sel.RB.value,
 333                                      in2, in2_isvec)
 334     print ("get_pdecode_idx_in in3", name, in3_sel, In3Sel.RS.value,
 335                                      in3, in3_isvec)
 336     # identify which regnames map to in1/2/3
 337     if name == 'RA':
 338         if (in1_sel == In1Sel.RA.value or
 339             (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
 340             return in1, in1_isvec
 341         if in1_sel == In1Sel.RA_OR_ZERO.value:
 342             return in1, in1_isvec
 343     elif name == 'RB':
 344         if in2_sel == In2Sel.RB.value:
 345             return in2, in2_isvec
 346         if in3_sel == In3Sel.RB.value:
 347             return in3, in3_isvec
 348     # XXX TODO, RC doesn't exist yet!
 349     elif name == 'RC':
 350         assert False, "RC does not exist yet"
 351     elif name == 'RS':
 352         if in1_sel == In1Sel.RS.value:
 353             return in1, in1_isvec
 354         if in2_sel == In2Sel.RS.value:
 355             return in2, in2_isvec
 356         if in3_sel == In3Sel.RS.value:
 357             return in3, in3_isvec
 358     return None, False
 359
 360
 361 def get_pdecode_cr_out(dec2, name):
 362     op = dec2.dec.op
 363     out_sel = yield op.cr_out
 364     out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
 365     sv_cr_out = yield op.sv_cr_out
 366     spec = yield dec2.crout_svdec.spec
 367     sv_override = yield dec2.dec_cr_out.sv_override
 368     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 369     out = yield dec2.e.write_cr.data
 370     o_isvec = yield dec2.o_isvec
 371     print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
 372     print ("    sv_cr_out", sv_cr_out)
 373     print ("    cr_bf", out_bitfield)
 374     print ("    spec", spec)
 375     print ("    override", sv_override)
 376     # identify which regnames map to out / o2
 377     if name == 'CR0':
 378         if out_sel == CROutSel.CR0.value:
 379             return out, o_isvec
 380     print ("get_pdecode_idx_out not found", name)
 381     return None, False
 382
 383
 384 def get_pdecode_idx_out(dec2, name):
 385     op = dec2.dec.op
 386     out_sel = yield op.out_sel
 387     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 388     out = yield dec2.e.write_reg.data
 389     o_isvec = yield dec2.o_isvec
 390     # identify which regnames map to out / o2
 391     if name == 'RA':
 392         print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
 393         if out_sel == OutSel.RA.value:
 394             return out, o_isvec
 395     elif name == 'RT':
 396         print ("get_pdecode_idx_out", out_sel, OutSel.RT.value,
 397                                       OutSel.RT_OR_ZERO.value, out, o_isvec)
 398         if out_sel == OutSel.RT.value:
 399             return out, o_isvec
 400     print ("get_pdecode_idx_out not found", name)
 401     return None, False
 402
 403
 404 # XXX TODO
 405 def get_pdecode_idx_out2(dec2, name):
 406     op = dec2.dec.op
 407     print ("TODO: get_pdecode_idx_out2", name)
 408     return None, False
 409
 410
 411 class ISACaller:
 412     # decoder2 - an instance of power_decoder2
 413     # regfile - a list of initial values for the registers
 414     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 415     # respect_pc - tracks the program counter.  requires initial_insns
 416     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 417                  initial_mem=None, initial_msr=0,
 418                  initial_svstate=0,
 419                  initial_insns=None, respect_pc=False,
 420                  disassembly=None,
 421                  initial_pc=0,
 422                  bigendian=False,
 423                  mmu=False):
 424
 425         self.bigendian = bigendian
 426         self.halted = False
 427         self.is_svp64_mode = False
 428         self.respect_pc = respect_pc
 429         if initial_sprs is None:
 430             initial_sprs = {}
 431         if initial_mem is None:
 432             initial_mem = {}
 433         if initial_insns is None:
 434             initial_insns = {}
 435             assert self.respect_pc == False, "instructions required to honor pc"
 436
 437         print("ISACaller insns", respect_pc, initial_insns, disassembly)
 438         print("ISACaller initial_msr", initial_msr)
 439
 440         # "fake program counter" mode (for unit testing)
 441         self.fake_pc = 0
 442         disasm_start = 0
 443         if not respect_pc:
 444             if isinstance(initial_mem, tuple):
 445                 self.fake_pc = initial_mem[0]
 446                 disasm_start = self.fake_pc
 447         else:
 448             disasm_start = initial_pc
 449
 450         # disassembly: we need this for now (not given from the decoder)
 451         self.disassembly = {}
 452         if disassembly:
 453             for i, code in enumerate(disassembly):
 454                 self.disassembly[i*4 + disasm_start] = code
 455
 456         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 457         self.svp64rm = SVP64RM()
 458         if initial_svstate is None:
 459             initial_svstate = 0
 460         if isinstance(initial_svstate, int):
 461             initial_svstate = SVP64State(initial_svstate)
 462         self.svstate = initial_svstate
 463         self.gpr = GPR(decoder2, self, self.svstate, regfile)
 464         self.spr = SPR(decoder2, initial_sprs) # initialise SPRs before MMU
 465         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 466         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 467         # MMU mode, redirect underlying Mem through RADIX
 468         if mmu:
 469             self.mem = RADIX(self.mem, self)
 470             self.imem = RADIX(self.imem, self)
 471         self.pc = PC()
 472         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 473
 474         # TODO, needed here:
 475         # FPR (same as GPR except for FP nums)
 476         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 477         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 478         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 479         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 480         #         -- Done
 481         # 2.3.2 LR   (actually SPR #8) -- Done
 482         # 2.3.3 CTR  (actually SPR #9) -- Done
 483         # 2.3.4 TAR  (actually SPR #815)
 484         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 485         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 486
 487         # create CR then allow portions of it to be "selectable" (below)
 488         #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
 489         self.cr = SelectableInt(initial_cr, 64)  # underlying reg
 490         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 491
 492         # "undefined", just set to variable-bit-width int (use exts "max")
 493         #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 494
 495         self.namespace = {}
 496         self.namespace.update(self.spr)
 497         self.namespace.update({'GPR': self.gpr,
 498                                'MEM': self.mem,
 499                                'SPR': self.spr,
 500                                'memassign': self.memassign,
 501                                'NIA': self.pc.NIA,
 502                                'CIA': self.pc.CIA,
 503                                'SVSTATE': self.svstate.spr,
 504                                'CR': self.cr,
 505                                'MSR': self.msr,
 506                                'undefined': undefined,
 507                                'mode_is_64bit': True,
 508                                'SO': XER_bits['SO']
 509                                })
 510
 511         # update pc to requested start point
 512         self.set_pc(initial_pc)
 513
 514         # field-selectable versions of Condition Register TODO check bitranges?
 515         self.crl = []
 516         for i in range(8):
 517             bits = tuple(range(i*4+32, (i+1)*4+32))  # errr... maybe?
 518             _cr = FieldSelectableInt(self.cr, bits)
 519             self.crl.append(_cr)
 520             self.namespace["CR%d" % i] = _cr
 521
 522         self.decoder = decoder2.dec
 523         self.dec2 = decoder2
 524
 525     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
 526         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
 527         # store CIA(+4?) in SRR0, set NIA to 0x700
 528         # store MSR in SRR1, set MSR to um errr something, have to check spec
 529         self.spr['SRR0'].value = self.pc.CIA.value
 530         self.spr['SRR1'].value = self.namespace['MSR'].value
 531         self.trap_nia = SelectableInt(trap_addr, 64)
 532         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 533
 534         # set exception bits.  TODO: this should, based on the address
 535         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
 536         # bits appropriately.  however it turns out that *for now* in all
 537         # cases (all trap_addrs) the exact same thing is needed.
 538         self.msr[MSRb.IR] = 0
 539         self.msr[MSRb.DR] = 0
 540         self.msr[MSRb.FE0] = 0
 541         self.msr[MSRb.FE1] = 0
 542         self.msr[MSRb.EE] = 0
 543         self.msr[MSRb.RI] = 0
 544         self.msr[MSRb.SF] = 1
 545         self.msr[MSRb.TM] = 0
 546         self.msr[MSRb.VEC] = 0
 547         self.msr[MSRb.VSX] = 0
 548         self.msr[MSRb.PR] = 0
 549         self.msr[MSRb.FP] = 0
 550         self.msr[MSRb.PMM] = 0
 551         self.msr[MSRb.TEs] = 0
 552         self.msr[MSRb.TEe] = 0
 553         self.msr[MSRb.UND] = 0
 554         self.msr[MSRb.LE] = 1
 555
 556     def memassign(self, ea, sz, val):
 557         self.mem.memassign(ea, sz, val)
 558
 559     def prep_namespace(self, formname, op_fields):
 560         # TODO: get field names from form in decoder*1* (not decoder2)
 561         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 562         # from spec
 563         # then "yield" fields only from op_fields rather than hard-coded
 564         # list, here.
 565         fields = self.decoder.sigforms[formname]
 566         for name in op_fields:
 567             if name == 'spr':
 568                 sig = getattr(fields, name.upper())
 569             else:
 570                 sig = getattr(fields, name)
 571             val = yield sig
 572             # these are all opcode fields involved in index-selection of CR,
 573             # and need to do "standard" arithmetic.  CR[BA+32] for example
 574             # would, if using SelectableInt, only be 5-bit.
 575             if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
 576                 self.namespace[name] = val
 577             else:
 578                 self.namespace[name] = SelectableInt(val, sig.width)
 579
 580         self.namespace['XER'] = self.spr['XER']
 581         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 582         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 583
 584     def handle_carry_(self, inputs, outputs, already_done):
 585         inv_a = yield self.dec2.e.do.invert_in
 586         if inv_a:
 587             inputs[0] = ~inputs[0]
 588
 589         imm_ok = yield self.dec2.e.do.imm_data.ok
 590         if imm_ok:
 591             imm = yield self.dec2.e.do.imm_data.data
 592             inputs.append(SelectableInt(imm, 64))
 593         assert len(outputs) >= 1
 594         print("outputs", repr(outputs))
 595         if isinstance(outputs, list) or isinstance(outputs, tuple):
 596             output = outputs[0]
 597         else:
 598             output = outputs
 599         gts = []
 600         for x in inputs:
 601             print("gt input", x, output)
 602             gt = (gtu(x, output))
 603             gts.append(gt)
 604         print(gts)
 605         cy = 1 if any(gts) else 0
 606         print("CA", cy, gts)
 607         if not (1 & already_done):
 608             self.spr['XER'][XER_bits['CA']] = cy
 609
 610         print("inputs", already_done, inputs)
 611         # 32 bit carry
 612         # ARGH... different for OP_ADD... *sigh*...
 613         op = yield self.dec2.e.do.insn_type
 614         if op == MicrOp.OP_ADD.value:
 615             res32 = (output.value & (1 << 32)) != 0
 616             a32 = (inputs[0].value & (1 << 32)) != 0
 617             if len(inputs) >= 2:
 618                 b32 = (inputs[1].value & (1 << 32)) != 0
 619             else:
 620                 b32 = False
 621             cy32 = res32 ^ a32 ^ b32
 622             print("CA32 ADD", cy32)
 623         else:
 624             gts = []
 625             for x in inputs:
 626                 print("input", x, output)
 627                 print("     x[32:64]", x, x[32:64])
 628                 print("     o[32:64]", output, output[32:64])
 629                 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
 630                 gts.append(gt)
 631             cy32 = 1 if any(gts) else 0
 632             print("CA32", cy32, gts)
 633         if not (2 & already_done):
 634             self.spr['XER'][XER_bits['CA32']] = cy32
 635
 636     def handle_overflow(self, inputs, outputs, div_overflow):
 637         if hasattr(self.dec2.e.do, "invert_in"):
 638             inv_a = yield self.dec2.e.do.invert_in
 639             if inv_a:
 640                 inputs[0] = ~inputs[0]
 641
 642         imm_ok = yield self.dec2.e.do.imm_data.ok
 643         if imm_ok:
 644             imm = yield self.dec2.e.do.imm_data.data
 645             inputs.append(SelectableInt(imm, 64))
 646         assert len(outputs) >= 1
 647         print("handle_overflow", inputs, outputs, div_overflow)
 648         if len(inputs) < 2 and div_overflow is None:
 649             return
 650
 651         # div overflow is different: it's returned by the pseudo-code
 652         # because it's more complex than can be done by analysing the output
 653         if div_overflow is not None:
 654             ov, ov32 = div_overflow, div_overflow
 655         # arithmetic overflow can be done by analysing the input and output
 656         elif len(inputs) >= 2:
 657             output = outputs[0]
 658
 659             # OV (64-bit)
 660             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 661             output_sgn = exts(output.value, output.bits) < 0
 662             ov = 1 if input_sgn[0] == input_sgn[1] and \
 663                 output_sgn != input_sgn[0] else 0
 664
 665             # OV (32-bit)
 666             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 667             output32_sgn = exts(output.value, 32) < 0
 668             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 669                 output32_sgn != input32_sgn[0] else 0
 670
 671         self.spr['XER'][XER_bits['OV']] = ov
 672         self.spr['XER'][XER_bits['OV32']] = ov32
 673         so = self.spr['XER'][XER_bits['SO']]
 674         so = so | ov
 675         self.spr['XER'][XER_bits['SO']] = so
 676
 677     def handle_comparison(self, outputs, cr_idx=0):
 678         out = outputs[0]
 679         assert isinstance(out, SelectableInt), \
 680             "out zero not a SelectableInt %s" % repr(outputs)
 681         print("handle_comparison", out.bits, hex(out.value))
 682         # TODO - XXX *processor* in 32-bit mode
 683         # https://bugs.libre-soc.org/show_bug.cgi?id=424
 684         # if is_32bit:
 685         #    o32 = exts(out.value, 32)
 686         #    print ("handle_comparison exts 32 bit", hex(o32))
 687         out = exts(out.value, out.bits)
 688         print("handle_comparison exts", hex(out))
 689         zero = SelectableInt(out == 0, 1)
 690         positive = SelectableInt(out > 0, 1)
 691         negative = SelectableInt(out < 0, 1)
 692         SO = self.spr['XER'][XER_bits['SO']]
 693         print("handle_comparison SO", SO)
 694         cr_field = selectconcat(negative, positive, zero, SO)
 695         self.crl[cr_idx].eq(cr_field)
 696
 697     def set_pc(self, pc_val):
 698         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 699         self.pc.update(self.namespace, self.is_svp64_mode)
 700
 701     def setup_one(self):
 702         """set up one instruction
 703         """
 704         if self.respect_pc:
 705             pc = self.pc.CIA.value
 706         else:
 707             pc = self.fake_pc
 708         self._pc = pc
 709         ins = self.imem.ld(pc, 4, False, True, instr_fetch=True)
 710         if ins is None:
 711             raise KeyError("no instruction at 0x%x" % pc)
 712         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 713         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 714
 715         yield self.dec2.sv_rm.eq(0)
 716         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 717         yield self.dec2.dec.bigendian.eq(self.bigendian)
 718         yield self.dec2.state.msr.eq(self.msr.value)
 719         yield self.dec2.state.pc.eq(pc)
 720         if self.svstate is not None:
 721             yield self.dec2.state.svstate.eq(self.svstate.spr.value)
 722
 723         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
 724         yield Settle()
 725         opcode = yield self.dec2.dec.opcode_in
 726         pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
 727         pfx.insn.value = opcode
 728         major = pfx.major.asint(msb0=True) # MSB0 inversion
 729         print ("prefix test: opcode:", major, bin(major),
 730                 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
 731         self.is_svp64_mode = ((major == 0b000001) and
 732                               pfx.insn[7].value == 0b1 and
 733                               pfx.insn[9].value == 0b1)
 734         self.pc.update_nia(self.is_svp64_mode)
 735         self.namespace['NIA'] = self.pc.NIA
 736         self.namespace['SVSTATE'] = self.svstate.spr
 737         if not self.is_svp64_mode:
 738             return
 739
 740         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
 741         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
 742         print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
 743         print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
 744         sv_rm = pfx.rm.asint(msb0=True)
 745         ins = self.imem.ld(pc+4, 4, False, True, instr_fetch=True)
 746         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
 747         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
 748         yield self.dec2.sv_rm.eq(sv_rm)                        # svp64 prefix
 749         yield Settle()
 750
 751     def execute_one(self):
 752         """execute one instruction
 753         """
 754         # get the disassembly code for this instruction
 755         if self.is_svp64_mode:
 756             code = self.disassembly[self._pc+4]
 757             print("    svp64 sim-execute", hex(self._pc), code)
 758         else:
 759             code = self.disassembly[self._pc]
 760             print("sim-execute", hex(self._pc), code)
 761         opname = code.split(' ')[0]
 762         yield from self.call(opname)
 763
 764         # don't use this except in special circumstances
 765         if not self.respect_pc:
 766             self.fake_pc += 4
 767
 768         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 769
 770     def get_assembly_name(self):
 771         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 772         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 773         dec_insn = yield self.dec2.e.do.insn
 774         asmcode = yield self.dec2.dec.op.asmcode
 775         print("get assembly name asmcode", asmcode, hex(dec_insn))
 776         asmop = insns.get(asmcode, None)
 777         int_op = yield self.dec2.dec.op.internal_op
 778
 779         # sigh reconstruct the assembly instruction name
 780         if hasattr(self.dec2.e.do, "oe"):
 781             ov_en = yield self.dec2.e.do.oe.oe
 782             ov_ok = yield self.dec2.e.do.oe.ok
 783         else:
 784             ov_en = False
 785             ov_ok = False
 786         if hasattr(self.dec2.e.do, "rc"):
 787             rc_en = yield self.dec2.e.do.rc.rc
 788             rc_ok = yield self.dec2.e.do.rc.ok
 789         else:
 790             rc_en = False
 791             rc_ok = False
 792         # grrrr have to special-case MUL op (see DecodeOE)
 793         print("ov %d en %d rc %d en %d op %d" %
 794               (ov_ok, ov_en, rc_ok, rc_en, int_op))
 795         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
 796             print("mul op")
 797             if rc_en & rc_ok:
 798                 asmop += "."
 799         else:
 800             if not asmop.endswith("."):  # don't add "." to "andis."
 801                 if rc_en & rc_ok:
 802                     asmop += "."
 803         if hasattr(self.dec2.e.do, "lk"):
 804             lk = yield self.dec2.e.do.lk
 805             if lk:
 806                 asmop += "l"
 807         print("int_op", int_op)
 808         if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
 809             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 810             print("AA", AA)
 811             if AA:
 812                 asmop += "a"
 813         spr_msb = yield from self.get_spr_msb()
 814         if int_op == MicrOp.OP_MFCR.value:
 815             if spr_msb:
 816                 asmop = 'mfocrf'
 817             else:
 818                 asmop = 'mfcr'
 819         # XXX TODO: for whatever weird reason this doesn't work
 820         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 821         if int_op == MicrOp.OP_MTCRF.value:
 822             if spr_msb:
 823                 asmop = 'mtocrf'
 824             else:
 825                 asmop = 'mtcrf'
 826         return asmop
 827
 828     def get_spr_msb(self):
 829         dec_insn = yield self.dec2.e.do.insn
 830         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 831
 832     def call(self, name):
 833         """call(opcode) - the primary execution point for instructions
 834         """
 835         name = name.strip()  # remove spaces if not already done so
 836         if self.halted:
 837             print("halted - not executing", name)
 838             return
 839
 840         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 841         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 842         asmop = yield from self.get_assembly_name()
 843         print("call", name, asmop)
 844
 845         # check privileged
 846         int_op = yield self.dec2.dec.op.internal_op
 847         spr_msb = yield from self.get_spr_msb()
 848
 849         instr_is_privileged = False
 850         if int_op in [MicrOp.OP_ATTN.value,
 851                       MicrOp.OP_MFMSR.value,
 852                       MicrOp.OP_MTMSR.value,
 853                       MicrOp.OP_MTMSRD.value,
 854                       # TODO: OP_TLBIE
 855                       MicrOp.OP_RFID.value]:
 856             instr_is_privileged = True
 857         if int_op in [MicrOp.OP_MFSPR.value,
 858                       MicrOp.OP_MTSPR.value] and spr_msb:
 859             instr_is_privileged = True
 860
 861         print("is priv", instr_is_privileged, hex(self.msr.value),
 862               self.msr[MSRb.PR])
 863         # check MSR priv bit and whether op is privileged: if so, throw trap
 864         if instr_is_privileged and self.msr[MSRb.PR] == 1:
 865             self.TRAP(0x700, PIb.PRIV)
 866             self.namespace['NIA'] = self.trap_nia
 867             self.pc.update(self.namespace, self.is_svp64_mode)
 868             return
 869
 870         # check halted condition
 871         if name == 'attn':
 872             self.halted = True
 873             return
 874
 875         # check illegal instruction
 876         illegal = False
 877         if name not in ['mtcrf', 'mtocrf']:
 878             illegal = name != asmop
 879
 880         # sigh deal with setvl not being supported by binutils (.long)
 881         if asmop.startswith('setvl'):
 882             illegal = False
 883             name = 'setvl'
 884
 885         if illegal:
 886             print("illegal", name, asmop)
 887             self.TRAP(0x700, PIb.ILLEG)
 888             self.namespace['NIA'] = self.trap_nia
 889             self.pc.update(self.namespace, self.is_svp64_mode)
 890             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
 891                   (name, asmop, self.pc.CIA.value))
 892             return
 893
 894         info = self.instrs[name]
 895         yield from self.prep_namespace(info.form, info.op_fields)
 896
 897         # preserve order of register names
 898         input_names = create_args(list(info.read_regs) +
 899                                   list(info.uninit_regs))
 900         print(input_names)
 901
 902         # get SVP64 entry for the current instruction
 903         sv_rm = self.svp64rm.instrs.get(name)
 904         if sv_rm is not None:
 905             dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
 906         else:
 907             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
 908         print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 909
 910         # get SVSTATE VL (oh and print out some debug stuff)
 911         if self.is_svp64_mode:
 912             vl = self.svstate.vl.asint(msb0=True)
 913             srcstep = self.svstate.srcstep.asint(msb0=True)
 914             dststep = self.svstate.srcstep.asint(msb0=True)
 915             sv_a_nz = yield self.dec2.sv_a_nz
 916             in1 = yield self.dec2.e.read_reg1.data
 917             print ("SVP64: VL, srcstep, dststep, sv_a_nz, in1",
 918                     vl, srcstep, dststep, sv_a_nz, in1)
 919
 920         # get predicate mask
 921         srcmask = dstmask = 0xffff_ffff_ffff_ffff
 922         if self.is_svp64_mode:
 923             pmode = yield self.dec2.rm_dec.predmode
 924             sv_ptype = yield self.dec2.dec.op.SV_Ptype
 925             srcpred = yield self.dec2.rm_dec.srcpred
 926             dstpred = yield self.dec2.rm_dec.dstpred
 927             if pmode == SVP64PredMode.INT.value:
 928                 srcmask = dstmask = get_predint(self.gpr, dstpred)
 929                 if sv_ptype == SVPtype.P2.value:
 930                     srcmask = get_predint(self.gpr, srcpred)
 931             elif pmode == SVP64PredMode.CR.value:
 932                 srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
 933                 if sv_ptype == SVPtype.P2.value:
 934                     srcmask = get_predcr(self.crl, srcpred, vl)
 935             print ("    pmode", pmode)
 936             print ("    ptype", sv_ptype)
 937             print ("    srcmask", bin(srcmask))
 938             print ("    dstmask", bin(dstmask))
 939
 940             # okaaay, so here we simply advance srcstep (TODO dststep)
 941             # until the predicate mask has a "1" bit... or we run out of VL
 942             # let srcstep==VL be the indicator to move to next instruction
 943             while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
 944                 print ("      skip", bin(1<<srcstep))
 945                 srcstep += 1
 946             # same for dststep
 947             while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
 948                 print ("      skip", bin(1<<dststep))
 949                 dststep += 1
 950
 951             # update SVSTATE with new srcstep
 952             self.svstate.srcstep[0:7] = srcstep
 953             self.svstate.dststep[0:7] = dststep
 954             self.namespace['SVSTATE'] = self.svstate.spr
 955             yield self.dec2.state.svstate.eq(self.svstate.spr.value)
 956             yield Settle() # let decoder update
 957             srcstep = self.svstate.srcstep.asint(msb0=True)
 958             dststep = self.svstate.dststep.asint(msb0=True)
 959             print ("    srcstep", srcstep)
 960             print ("    dststep", dststep)
 961
 962             # check if end reached (we let srcstep overrun, above)
 963             # nothing needs doing (TODO zeroing): just do next instruction
 964             if srcstep == vl:
 965                 self.svp64_reset_loop()
 966                 self.update_pc_next()
 967                 return
 968
 969         # VL=0 in SVP64 mode means "do nothing: skip instruction"
 970         if self.is_svp64_mode and vl == 0:
 971             self.pc.update(self.namespace, self.is_svp64_mode)
 972             print("SVP64: VL=0, end of call", self.namespace['CIA'],
 973                                        self.namespace['NIA'])
 974             return
 975
 976         # main input registers (RT, RA ...)
 977         inputs = []
 978         for name in input_names:
 979             # using PowerDecoder2, first, find the decoder index.
 980             # (mapping name RA RB RC RS to in1, in2, in3)
 981             regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
 982             if regnum is None:
 983                 # doing this is not part of svp64, it's because output
 984                 # registers, to be modified, need to be in the namespace.
 985                 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
 986
 987             # in case getting the register number is needed, _RA, _RB
 988             regname = "_" + name
 989             self.namespace[regname] = regnum
 990             print('reading reg %s %s' % (name, str(regnum)), is_vec)
 991             reg_val = self.gpr(regnum)
 992             inputs.append(reg_val)
 993
 994         # "special" registers
 995         for special in info.special_regs:
 996             if special in special_sprs:
 997                 inputs.append(self.spr[special])
 998             else:
 999                 inputs.append(self.namespace[special])
1000
1001         # clear trap (trap) NIA
1002         self.trap_nia = None
1003
1004         # execute actual instruction here
1005         print("inputs", inputs)
1006         results = info.func(self, *inputs)
1007         print("results", results)
1008
1009         # "inject" decorator takes namespace from function locals: we need to
1010         # overwrite NIA being overwritten (sigh)
1011         if self.trap_nia is not None:
1012             self.namespace['NIA'] = self.trap_nia
1013
1014         print("after func", self.namespace['CIA'], self.namespace['NIA'])
1015
1016         # detect if CA/CA32 already in outputs (sra*, basically)
1017         already_done = 0
1018         if info.write_regs:
1019             output_names = create_args(info.write_regs)
1020             for name in output_names:
1021                 if name == 'CA':
1022                     already_done |= 1
1023                 if name == 'CA32':
1024                     already_done |= 2
1025
1026         print("carry already done?", bin(already_done))
1027         if hasattr(self.dec2.e.do, "output_carry"):
1028             carry_en = yield self.dec2.e.do.output_carry
1029         else:
1030             carry_en = False
1031         if carry_en:
1032             yield from self.handle_carry_(inputs, results, already_done)
1033
1034         # detect if overflow was in return result
1035         overflow = None
1036         if info.write_regs:
1037             for name, output in zip(output_names, results):
1038                 if name == 'overflow':
1039                     overflow = output
1040
1041         if hasattr(self.dec2.e.do, "oe"):
1042             ov_en = yield self.dec2.e.do.oe.oe
1043             ov_ok = yield self.dec2.e.do.oe.ok
1044         else:
1045             ov_en = False
1046             ov_ok = False
1047         print("internal overflow", overflow, ov_en, ov_ok)
1048         if ov_en & ov_ok:
1049             yield from self.handle_overflow(inputs, results, overflow)
1050
1051         if hasattr(self.dec2.e.do, "rc"):
1052             rc_en = yield self.dec2.e.do.rc.rc
1053         else:
1054             rc_en = False
1055         if rc_en:
1056             regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
1057             self.handle_comparison(results, regnum)
1058
1059         # any modified return results?
1060         if info.write_regs:
1061             for name, output in zip(output_names, results):
1062                 if name == 'overflow':  # ignore, done already (above)
1063                     continue
1064                 if isinstance(output, int):
1065                     output = SelectableInt(output, 256)
1066                 if name in ['CA', 'CA32']:
1067                     if carry_en:
1068                         print("writing %s to XER" % name, output)
1069                         self.spr['XER'][XER_bits[name]] = output.value
1070                     else:
1071                         print("NOT writing %s to XER" % name, output)
1072                 elif name in info.special_regs:
1073                     print('writing special %s' % name, output, special_sprs)
1074                     if name in special_sprs:
1075                         self.spr[name] = output
1076                     else:
1077                         self.namespace[name].eq(output)
1078                     if name == 'MSR':
1079                         print('msr written', hex(self.msr.value))
1080                 else:
1081                     regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
1082                                                 name)
1083                     if regnum is None:
1084                         # temporary hack for not having 2nd output
1085                         regnum = yield getattr(self.decoder, name)
1086                         is_vec = False
1087                     print('writing reg %d %s' % (regnum, str(output)), is_vec)
1088                     if output.bits > 64:
1089                         output = SelectableInt(output.value, 64)
1090                     self.gpr[regnum] = output
1091
1092         # check if it is the SVSTATE.src/dest step that needs incrementing
1093         # this is our Sub-Program-Counter loop from 0 to VL-1
1094         if self.is_svp64_mode:
1095             # XXX twin predication TODO
1096             vl = self.svstate.vl.asint(msb0=True)
1097             mvl = self.svstate.maxvl.asint(msb0=True)
1098             srcstep = self.svstate.srcstep.asint(msb0=True)
1099             dststep = self.svstate.srcstep.asint(msb0=True)
1100             sv_ptype = yield self.dec2.dec.op.SV_Ptype
1101             no_out_vec = not (yield self.dec2.no_out_vec)
1102             no_in_vec = not (yield self.dec2.no_in_vec)
1103             print ("    svstate.vl", vl)
1104             print ("    svstate.mvl", mvl)
1105             print ("    svstate.srcstep", srcstep)
1106             print ("    svstate.dststep", dststep)
1107             print ("    no_out_vec", no_out_vec)
1108             print ("    no_in_vec", no_in_vec)
1109             print ("    sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
1110             # check if srcstep needs incrementing by one, stop PC advancing
1111             # svp64 loop can end early if the dest is scalar for single-pred
1112             # but for 2-pred both src/dest have to be checked.
1113             # XXX this might not be true! it may just be LD/ST
1114             if sv_ptype == SVPtype.P2.value:
1115                 svp64_is_vector = (no_out_vec or no_in_vec)
1116             else:
1117                 svp64_is_vector = no_out_vec
1118             if svp64_is_vector and srcstep != vl-1:
1119                 self.svstate.srcstep += SelectableInt(1, 7)
1120                 self.svstate.dststep += SelectableInt(1, 7)
1121                 self.pc.NIA.value = self.pc.CIA.value
1122                 self.namespace['NIA'] = self.pc.NIA
1123                 self.namespace['SVSTATE'] = self.svstate.spr
1124                 print("end of sub-pc call", self.namespace['CIA'],
1125                                      self.namespace['NIA'])
1126                 return # DO NOT allow PC to update whilst Sub-PC loop running
1127             # reset loop to zero
1128             self.svp64_reset_loop()
1129
1130         self.update_pc_next()
1131
1132     def update_pc_next(self):
1133         # UPDATE program counter
1134         self.pc.update(self.namespace, self.is_svp64_mode)
1135         self.svstate.spr = self.namespace['SVSTATE']
1136         print("end of call", self.namespace['CIA'],
1137                              self.namespace['NIA'],
1138                              self.namespace['SVSTATE'])
1139
1140     def svp64_reset_loop(self):
1141         self.svstate.srcstep[0:7] = 0
1142         self.svstate.dststep[0:7] = 0
1143         print ("    svstate.srcstep loop end (PC to update)")
1144         self.pc.update_nia(self.is_svp64_mode)
1145         self.namespace['NIA'] = self.pc.NIA
1146         self.namespace['SVSTATE'] = self.svstate.spr
1147
1148 def inject():
1149     """Decorator factory.
1150
1151     this decorator will "inject" variables into the function's namespace,
1152     from the *dictionary* in self.namespace.  it therefore becomes possible
1153     to make it look like a whole stack of variables which would otherwise
1154     need "self." inserted in front of them (*and* for those variables to be
1155     added to the instance) "appear" in the function.
1156
1157     "self.namespace['SI']" for example becomes accessible as just "SI" but
1158     *only* inside the function, when decorated.
1159     """
1160     def variable_injector(func):
1161         @wraps(func)
1162         def decorator(*args, **kwargs):
1163             try:
1164                 func_globals = func.__globals__  # Python 2.6+
1165             except AttributeError:
1166                 func_globals = func.func_globals  # Earlier versions.
1167
1168             context = args[0].namespace  # variables to be injected
1169             saved_values = func_globals.copy()  # Shallow copy of dict.
1170             func_globals.update(context)
1171             result = func(*args, **kwargs)
1172             print("globals after", func_globals['CIA'], func_globals['NIA'])
1173             print("args[0]", args[0].namespace['CIA'],
1174                   args[0].namespace['NIA'],
1175                   args[0].namespace['SVSTATE'])
1176             args[0].namespace = func_globals
1177             #exec (func.__code__, func_globals)
1178
1179             # finally:
1180             #    func_globals = saved_values  # Undo changes.
1181
1182             return result
1183
1184         return decorator
1185
1186     return variable_injector
1187
1188