src/soc/decoder/isa/caller.py

   1 """core of the python-based POWER9 simulator
   2
   3 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   4 not speed, it is for both learning and educational purposes, as well as
   5 a method of verifying the HDL.
   6
   7 related bugs:
   8
   9 * https://bugs.libre-soc.org/show_bug.cgi?id=424
  10 """
  11
  12 from functools import wraps
  13 from copy import copy
  14 from soc.decoder.orderedset import OrderedSet
  15 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  16                                         selectconcat)
  17 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
  18                                      insns, MicrOp)
  19 from soc.decoder.helpers import exts, gtu, ltu
  20 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
  21
  22 from collections import namedtuple
  23 import math
  24 import sys
  25
  26 instruction_info = namedtuple('instruction_info',
  27                               'func read_regs uninit_regs write_regs ' +
  28                               'special_regs op_fields form asmregs')
  29
  30 special_sprs = {
  31     'LR': 8,
  32     'CTR': 9,
  33     'TAR': 815,
  34     'XER': 1,
  35     'VRSAVE': 256}
  36
  37
  38 def swap_order(x, nbytes):
  39     x = x.to_bytes(nbytes, byteorder='little')
  40     x = int.from_bytes(x, byteorder='big', signed=False)
  41     return x
  42
  43
  44 def create_args(reglist, extra=None):
  45     args = OrderedSet()
  46     for reg in reglist:
  47         args.add(reg)
  48     args = list(args)
  49     if extra:
  50         args = [extra] + args
  51     return args
  52
  53
  54 class Mem:
  55
  56     def __init__(self, row_bytes=8, initial_mem=None):
  57         self.mem = {}
  58         self.bytes_per_word = row_bytes
  59         self.word_log2 = math.ceil(math.log2(row_bytes))
  60         print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
  61         if not initial_mem:
  62             return
  63
  64         # different types of memory data structures recognised (for convenience)
  65         if isinstance(initial_mem, list):
  66             initial_mem = (0, initial_mem)
  67         if isinstance(initial_mem, tuple):
  68             startaddr, mem = initial_mem
  69             initial_mem = {}
  70             for i, val in enumerate(mem):
  71                 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
  72
  73         for addr, (val, width) in initial_mem.items():
  74             #val = swap_order(val, width)
  75             self.st(addr, val, width, swap=False)
  76
  77     def _get_shifter_mask(self, wid, remainder):
  78         shifter = ((self.bytes_per_word - wid) - remainder) * \
  79             8  # bits per byte
  80         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
  81         # BE/LE mode?
  82         shifter = remainder * 8
  83         mask = (1 << (wid * 8)) - 1
  84         print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
  85         return shifter, mask
  86
  87     # TODO: Implement ld/st of lesser width
  88     def ld(self, address, width=8, swap=True, check_in_mem=False):
  89         print("ld from addr 0x{:x} width {:d}".format(address, width))
  90         remainder = address & (self.bytes_per_word - 1)
  91         address = address >> self.word_log2
  92         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  93         if address in self.mem:
  94             val = self.mem[address]
  95         elif check_in_mem:
  96             return None
  97         else:
  98             val = 0
  99         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
 100
 101         if width != self.bytes_per_word:
 102             shifter, mask = self._get_shifter_mask(width, remainder)
 103             print("masking", hex(val), hex(mask << shifter), shifter)
 104             val = val & (mask << shifter)
 105             val >>= shifter
 106         if swap:
 107             val = swap_order(val, width)
 108         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
 109         return val
 110
 111     def st(self, addr, v, width=8, swap=True):
 112         staddr = addr
 113         remainder = addr & (self.bytes_per_word - 1)
 114         addr = addr >> self.word_log2
 115         print("Writing 0x{:x} to ST 0x{:x} "
 116               "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
 117         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 118         if swap:
 119             v = swap_order(v, width)
 120         if width != self.bytes_per_word:
 121             if addr in self.mem:
 122                 val = self.mem[addr]
 123             else:
 124                 val = 0
 125             shifter, mask = self._get_shifter_mask(width, remainder)
 126             val &= ~(mask << shifter)
 127             val |= v << shifter
 128             self.mem[addr] = val
 129         else:
 130             self.mem[addr] = v
 131         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 132
 133     def __call__(self, addr, sz):
 134         val = self.ld(addr.value, sz, swap=False)
 135         print("memread", addr, sz, val)
 136         return SelectableInt(val, sz*8)
 137
 138     def memassign(self, addr, sz, val):
 139         print("memassign", addr, sz, val)
 140         self.st(addr.value, val.value, sz, swap=False)
 141
 142
 143 class GPR(dict):
 144     def __init__(self, decoder, regfile):
 145         dict.__init__(self)
 146         self.sd = decoder
 147         for i in range(32):
 148             self[i] = SelectableInt(regfile[i], 64)
 149
 150     def __call__(self, ridx):
 151         return self[ridx]
 152
 153     def set_form(self, form):
 154         self.form = form
 155
 156     def getz(self, rnum):
 157         # rnum = rnum.value # only SelectableInt allowed
 158         print("GPR getzero", rnum)
 159         if rnum == 0:
 160             return SelectableInt(0, 64)
 161         return self[rnum]
 162
 163     def _get_regnum(self, attr):
 164         getform = self.sd.sigforms[self.form]
 165         rnum = getattr(getform, attr)
 166         return rnum
 167
 168     def ___getitem__(self, attr):
 169         print("GPR getitem", attr)
 170         rnum = self._get_regnum(attr)
 171         return self.regfile[rnum]
 172
 173     def dump(self):
 174         for i in range(0, len(self), 8):
 175             s = []
 176             for j in range(8):
 177                 s.append("%08x" % self[i+j].value)
 178             s = ' '.join(s)
 179             print("reg", "%2d" % i, s)
 180
 181
 182 class PC:
 183     def __init__(self, pc_init=0):
 184         self.CIA = SelectableInt(pc_init, 64)
 185         self.NIA = self.CIA + SelectableInt(4, 64)
 186
 187     def update(self, namespace):
 188         self.CIA = namespace['NIA'].narrow(64)
 189         self.NIA = self.CIA + SelectableInt(4, 64)
 190         namespace['CIA'] = self.CIA
 191         namespace['NIA'] = self.NIA
 192
 193
 194 class SPR(dict):
 195     def __init__(self, dec2, initial_sprs={}):
 196         self.sd = dec2
 197         dict.__init__(self)
 198         for key, v in initial_sprs.items():
 199             if isinstance(key, SelectableInt):
 200                 key = key.value
 201             key = special_sprs.get(key, key)
 202             if isinstance(key, int):
 203                 info = spr_dict[key]
 204             else:
 205                 info = spr_byname[key]
 206             if not isinstance(v, SelectableInt):
 207                 v = SelectableInt(v, info.length)
 208             self[key] = v
 209
 210     def __getitem__(self, key):
 211         print("get spr", key)
 212         print("dict", self.items())
 213         # if key in special_sprs get the special spr, otherwise return key
 214         if isinstance(key, SelectableInt):
 215             key = key.value
 216         if isinstance(key, int):
 217             key = spr_dict[key].SPR
 218         key = special_sprs.get(key, key)
 219         if key == 'HSRR0': # HACK!
 220             key = 'SRR0'
 221         if key == 'HSRR1': # HACK!
 222             key = 'SRR1'
 223         if key in self:
 224             res = dict.__getitem__(self, key)
 225         else:
 226             if isinstance(key, int):
 227                 info = spr_dict[key]
 228             else:
 229                 info = spr_byname[key]
 230             dict.__setitem__(self, key, SelectableInt(0, info.length))
 231             res = dict.__getitem__(self, key)
 232         print("spr returning", key, res)
 233         return res
 234
 235     def __setitem__(self, key, value):
 236         if isinstance(key, SelectableInt):
 237             key = key.value
 238         if isinstance(key, int):
 239             key = spr_dict[key].SPR
 240             print("spr key", key)
 241         key = special_sprs.get(key, key)
 242         if key == 'HSRR0': # HACK!
 243             self.__setitem__('SRR0', value)
 244         if key == 'HSRR1': # HACK!
 245             self.__setitem__('SRR1', value)
 246         print("setting spr", key, value)
 247         dict.__setitem__(self, key, value)
 248
 249     def __call__(self, ridx):
 250         return self[ridx]
 251
 252
 253 class ISACaller:
 254     # decoder2 - an instance of power_decoder2
 255     # regfile - a list of initial values for the registers
 256     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 257     # respect_pc - tracks the program counter.  requires initial_insns
 258     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 259                  initial_mem=None, initial_msr=0,
 260                  initial_insns=None, respect_pc=False,
 261                  disassembly=None,
 262                  initial_pc=0,
 263                  bigendian=False):
 264
 265         self.bigendian = bigendian
 266         self.halted = False
 267         self.respect_pc = respect_pc
 268         if initial_sprs is None:
 269             initial_sprs = {}
 270         if initial_mem is None:
 271             initial_mem = {}
 272         if initial_insns is None:
 273             initial_insns = {}
 274             assert self.respect_pc == False, "instructions required to honor pc"
 275
 276         print("ISACaller insns", respect_pc, initial_insns, disassembly)
 277         print("ISACaller initial_msr", initial_msr)
 278
 279         # "fake program counter" mode (for unit testing)
 280         self.fake_pc = 0
 281         disasm_start = 0
 282         if not respect_pc:
 283             if isinstance(initial_mem, tuple):
 284                 self.fake_pc = initial_mem[0]
 285                 disasm_start = self.fake_pc
 286         else:
 287             disasm_start = initial_pc
 288
 289         # disassembly: we need this for now (not given from the decoder)
 290         self.disassembly = {}
 291         if disassembly:
 292             for i, code in enumerate(disassembly):
 293                 self.disassembly[i*4 + disasm_start] = code
 294
 295         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 296         self.gpr = GPR(decoder2, regfile)
 297         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 298         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 299         self.pc = PC()
 300         self.spr = SPR(decoder2, initial_sprs)
 301         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 302
 303         # TODO, needed here:
 304         # FPR (same as GPR except for FP nums)
 305         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 306         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 307         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 308         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 309         #         -- Done
 310         # 2.3.2 LR   (actually SPR #8) -- Done
 311         # 2.3.3 CTR  (actually SPR #9) -- Done
 312         # 2.3.4 TAR  (actually SPR #815)
 313         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 314         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 315
 316         # create CR then allow portions of it to be "selectable" (below)
 317         self._cr = SelectableInt(initial_cr, 64)  # underlying reg
 318         self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 319
 320         # "undefined", just set to variable-bit-width int (use exts "max")
 321         self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 322
 323         self.namespace = {}
 324         self.namespace.update(self.spr)
 325         self.namespace.update({'GPR': self.gpr,
 326                                'MEM': self.mem,
 327                                'SPR': self.spr,
 328                                'memassign': self.memassign,
 329                                'NIA': self.pc.NIA,
 330                                'CIA': self.pc.CIA,
 331                                'CR': self.cr,
 332                                'MSR': self.msr,
 333                                'undefined': self.undefined,
 334                                'mode_is_64bit': True,
 335                                'SO': XER_bits['SO']
 336                                })
 337
 338         # update pc to requested start point
 339         self.set_pc(initial_pc)
 340
 341         # field-selectable versions of Condition Register TODO check bitranges?
 342         self.crl = []
 343         for i in range(8):
 344             bits = tuple(range(i*4, (i+1)*4))  # errr... maybe?
 345             _cr = FieldSelectableInt(self.cr, bits)
 346             self.crl.append(_cr)
 347             self.namespace["CR%d" % i] = _cr
 348
 349         self.decoder = decoder2.dec
 350         self.dec2 = decoder2
 351
 352     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
 353         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
 354         # store CIA(+4?) in SRR0, set NIA to 0x700
 355         # store MSR in SRR1, set MSR to um errr something, have to check spec
 356         self.spr['SRR0'].value = self.pc.CIA.value
 357         self.spr['SRR1'].value = self.namespace['MSR'].value
 358         self.trap_nia = SelectableInt(trap_addr, 64)
 359         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 360
 361         # set exception bits.  TODO: this should, based on the address
 362         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
 363         # bits appropriately.  however it turns out that *for now* in all
 364         # cases (all trap_addrs) the exact same thing is needed.
 365         self.msr[MSRb.IR] = 0
 366         self.msr[MSRb.DR] = 0
 367         self.msr[MSRb.FE0] = 0
 368         self.msr[MSRb.FE1] = 0
 369         self.msr[MSRb.EE] = 0
 370         self.msr[MSRb.RI] = 0
 371         self.msr[MSRb.SF] = 1
 372         self.msr[MSRb.TM] = 0
 373         self.msr[MSRb.VEC] = 0
 374         self.msr[MSRb.VSX] = 0
 375         self.msr[MSRb.PR] = 0
 376         self.msr[MSRb.FP] = 0
 377         self.msr[MSRb.PMM] = 0
 378         self.msr[MSRb.TEs] = 0
 379         self.msr[MSRb.TEe] = 0
 380         self.msr[MSRb.UND] = 0
 381         self.msr[MSRb.LE] = 1
 382
 383     def memassign(self, ea, sz, val):
 384         self.mem.memassign(ea, sz, val)
 385
 386     def prep_namespace(self, formname, op_fields):
 387         # TODO: get field names from form in decoder*1* (not decoder2)
 388         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 389         # from spec
 390         # then "yield" fields only from op_fields rather than hard-coded
 391         # list, here.
 392         fields = self.decoder.sigforms[formname]
 393         for name in op_fields:
 394             if name == 'spr':
 395                 sig = getattr(fields, name.upper())
 396             else:
 397                 sig = getattr(fields, name)
 398             val = yield sig
 399             if name in ['BF', 'BFA']:
 400                 self.namespace[name] = val
 401             else:
 402                 self.namespace[name] = SelectableInt(val, sig.width)
 403
 404         self.namespace['XER'] = self.spr['XER']
 405         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 406         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 407
 408     def handle_carry_(self, inputs, outputs, already_done):
 409         inv_a = yield self.dec2.e.do.invert_a
 410         if inv_a:
 411             inputs[0] = ~inputs[0]
 412
 413         imm_ok = yield self.dec2.e.do.imm_data.ok
 414         if imm_ok:
 415             imm = yield self.dec2.e.do.imm_data.data
 416             inputs.append(SelectableInt(imm, 64))
 417         assert len(outputs) >= 1
 418         print("outputs", repr(outputs))
 419         if isinstance(outputs, list) or isinstance(outputs, tuple):
 420             output = outputs[0]
 421         else:
 422             output = outputs
 423         gts = []
 424         for x in inputs:
 425             print("gt input", x, output)
 426             gt = (gtu(x, output))
 427             gts.append(gt)
 428         print(gts)
 429         cy = 1 if any(gts) else 0
 430         if not (1 & already_done):
 431             self.spr['XER'][XER_bits['CA']] = cy
 432
 433         print("inputs", inputs)
 434         # 32 bit carry
 435         gts = []
 436         for x in inputs:
 437             print("input", x, output)
 438             gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
 439             gts.append(gt)
 440         cy32 = 1 if any(gts) else 0
 441         if not (2 & already_done):
 442             self.spr['XER'][XER_bits['CA32']] = cy32
 443
 444     def handle_overflow(self, inputs, outputs, div_overflow):
 445         inv_a = yield self.dec2.e.do.invert_a
 446         if inv_a:
 447             inputs[0] = ~inputs[0]
 448
 449         imm_ok = yield self.dec2.e.do.imm_data.ok
 450         if imm_ok:
 451             imm = yield self.dec2.e.do.imm_data.data
 452             inputs.append(SelectableInt(imm, 64))
 453         assert len(outputs) >= 1
 454         print("handle_overflow", inputs, outputs, div_overflow)
 455         if len(inputs) < 2 and div_overflow is None:
 456             return
 457
 458         # div overflow is different: it's returned by the pseudo-code
 459         # because it's more complex than can be done by analysing the output
 460         if div_overflow is not None:
 461             ov, ov32 = div_overflow, div_overflow
 462         # arithmetic overflow can be done by analysing the input and output
 463         elif len(inputs) >= 2:
 464             output = outputs[0]
 465
 466             # OV (64-bit)
 467             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 468             output_sgn = exts(output.value, output.bits) < 0
 469             ov = 1 if input_sgn[0] == input_sgn[1] and \
 470                 output_sgn != input_sgn[0] else 0
 471
 472             # OV (32-bit)
 473             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 474             output32_sgn = exts(output.value, 32) < 0
 475             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 476                 output32_sgn != input32_sgn[0] else 0
 477
 478         self.spr['XER'][XER_bits['OV']] = ov
 479         self.spr['XER'][XER_bits['OV32']] = ov32
 480         so = self.spr['XER'][XER_bits['SO']]
 481         so = so | ov
 482         self.spr['XER'][XER_bits['SO']] = so
 483
 484     def handle_comparison(self, outputs):
 485         out = outputs[0]
 486         assert isinstance(out, SelectableInt), \
 487                           "out zero not a SelectableInt %s" % repr(outputs)
 488         print("handle_comparison", out.bits, hex(out.value))
 489         # TODO - XXX *processor* in 32-bit mode
 490         # https://bugs.libre-soc.org/show_bug.cgi?id=424
 491         # if is_32bit:
 492         #    o32 = exts(out.value, 32)
 493         #    print ("handle_comparison exts 32 bit", hex(o32))
 494         out = exts(out.value, out.bits)
 495         print("handle_comparison exts", hex(out))
 496         zero = SelectableInt(out == 0, 1)
 497         positive = SelectableInt(out > 0, 1)
 498         negative = SelectableInt(out < 0, 1)
 499         SO = self.spr['XER'][XER_bits['SO']]
 500         print("handle_comparison SO", SO)
 501         cr_field = selectconcat(negative, positive, zero, SO)
 502         self.crl[0].eq(cr_field)
 503
 504     def set_pc(self, pc_val):
 505         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 506         self.pc.update(self.namespace)
 507
 508     def setup_one(self):
 509         """set up one instruction
 510         """
 511         if self.respect_pc:
 512             pc = self.pc.CIA.value
 513         else:
 514             pc = self.fake_pc
 515         self._pc = pc
 516         ins = self.imem.ld(pc, 4, False, True)
 517         if ins is None:
 518             raise KeyError("no instruction at 0x%x" % pc)
 519         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 520         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 521
 522         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 523         yield self.dec2.dec.bigendian.eq(self.bigendian)
 524         yield self.dec2.state.msr.eq(self.msr.value)
 525         yield self.dec2.state.pc.eq(pc)
 526
 527     def execute_one(self):
 528         """execute one instruction
 529         """
 530         # get the disassembly code for this instruction
 531         code = self.disassembly[self._pc]
 532         print("sim-execute", hex(self._pc), code)
 533         opname = code.split(' ')[0]
 534         yield from self.call(opname)
 535
 536         if not self.respect_pc:
 537             self.fake_pc += 4
 538         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 539
 540     def get_assembly_name(self):
 541         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 542         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 543         dec_insn = yield self.dec2.e.do.insn
 544         asmcode = yield self.dec2.dec.op.asmcode
 545         print("get assembly name asmcode", asmcode, hex(dec_insn))
 546         asmop = insns.get(asmcode, None)
 547         int_op = yield self.dec2.dec.op.internal_op
 548
 549         # sigh reconstruct the assembly instruction name
 550         ov_en = yield self.dec2.e.do.oe.oe
 551         ov_ok = yield self.dec2.e.do.oe.ok
 552         rc_en = yield self.dec2.e.do.rc.data
 553         rc_ok = yield self.dec2.e.do.rc.ok
 554         # grrrr have to special-case MUL op (see DecodeOE)
 555         print("ov %d en %d rc %d en %d op %d" % \
 556                         (ov_ok, ov_en, rc_ok, rc_en, int_op))
 557         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
 558             print("mul op")
 559             if rc_en & rc_ok:
 560                 asmop += "."
 561         else:
 562             if not asmop.endswith("."): # don't add "." to "andis."
 563                 if rc_en & rc_ok:
 564                     asmop += "."
 565         lk = yield self.dec2.e.do.lk
 566         if lk:
 567             asmop += "l"
 568         print("int_op", int_op)
 569         if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
 570             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 571             print("AA", AA)
 572             if AA:
 573                 asmop += "a"
 574         spr_msb = yield from self.get_spr_msb()
 575         if int_op == MicrOp.OP_MFCR.value:
 576             if spr_msb:
 577                 asmop = 'mfocrf'
 578             else:
 579                 asmop = 'mfcr'
 580         # XXX TODO: for whatever weird reason this doesn't work
 581         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 582         if int_op == MicrOp.OP_MTCRF.value:
 583             if spr_msb:
 584                 asmop = 'mtocrf'
 585             else:
 586                 asmop = 'mtcrf'
 587         return asmop
 588
 589     def get_spr_msb(self):
 590         dec_insn = yield self.dec2.e.do.insn
 591         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 592
 593     def call(self, name):
 594         name = name.strip()  # remove spaces if not already done so
 595         if self.halted:
 596             print("halted - not executing", name)
 597             return
 598
 599         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 600         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 601         asmop = yield from self.get_assembly_name()
 602         print("call", name, asmop)
 603
 604         # check privileged
 605         int_op = yield self.dec2.dec.op.internal_op
 606         spr_msb = yield from self.get_spr_msb()
 607
 608         instr_is_privileged = False
 609         if int_op in [MicrOp.OP_ATTN.value,
 610                       MicrOp.OP_MFMSR.value,
 611                       MicrOp.OP_MTMSR.value,
 612                       MicrOp.OP_MTMSRD.value,
 613                       # TODO: OP_TLBIE
 614                       MicrOp.OP_RFID.value]:
 615             instr_is_privileged = True
 616         if int_op in [MicrOp.OP_MFSPR.value,
 617                       MicrOp.OP_MTSPR.value] and spr_msb:
 618             instr_is_privileged = True
 619
 620         print("is priv", instr_is_privileged, hex(self.msr.value),
 621               self.msr[MSRb.PR])
 622         # check MSR priv bit and whether op is privileged: if so, throw trap
 623         if instr_is_privileged and self.msr[MSRb.PR] == 1:
 624             self.TRAP(0x700, PIb.PRIV)
 625             self.namespace['NIA'] = self.trap_nia
 626             self.pc.update(self.namespace)
 627             return
 628
 629         # check halted condition
 630         if name == 'attn':
 631             self.halted = True
 632             return
 633
 634         # check illegal instruction
 635         illegal = False
 636         if name not in ['mtcrf', 'mtocrf']:
 637             illegal = name != asmop
 638
 639         if illegal:
 640             print ("illegal", name, asmop)
 641             self.TRAP(0x700, PIb.ILLEG)
 642             self.namespace['NIA'] = self.trap_nia
 643             self.pc.update(self.namespace)
 644             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
 645                   (name, asmop, self.pc.CIA.value))
 646             return
 647
 648         info = self.instrs[name]
 649         yield from self.prep_namespace(info.form, info.op_fields)
 650
 651         # preserve order of register names
 652         input_names = create_args(list(info.read_regs) +
 653                                   list(info.uninit_regs))
 654         print(input_names)
 655
 656         # main registers (RT, RA ...)
 657         inputs = []
 658         for name in input_names:
 659             regnum = yield getattr(self.decoder, name)
 660             regname = "_" + name
 661             self.namespace[regname] = regnum
 662             print('reading reg %d' % regnum)
 663             inputs.append(self.gpr(regnum))
 664
 665         # "special" registers
 666         for special in info.special_regs:
 667             if special in special_sprs:
 668                 inputs.append(self.spr[special])
 669             else:
 670                 inputs.append(self.namespace[special])
 671
 672         # clear trap (trap) NIA
 673         self.trap_nia = None
 674
 675         print(inputs)
 676         results = info.func(self, *inputs)
 677         print(results)
 678
 679         # "inject" decorator takes namespace from function locals: we need to
 680         # overwrite NIA being overwritten (sigh)
 681         if self.trap_nia is not None:
 682             self.namespace['NIA'] = self.trap_nia
 683
 684         print("after func", self.namespace['CIA'], self.namespace['NIA'])
 685
 686         # detect if CA/CA32 already in outputs (sra*, basically)
 687         already_done = 0
 688         if info.write_regs:
 689             output_names = create_args(info.write_regs)
 690             for name in output_names:
 691                 if name == 'CA':
 692                     already_done |= 1
 693                 if name == 'CA32':
 694                     already_done |= 2
 695
 696         print("carry already done?", bin(already_done))
 697         carry_en = yield self.dec2.e.do.output_carry
 698         if carry_en:
 699             yield from self.handle_carry_(inputs, results, already_done)
 700
 701         # detect if overflow was in return result
 702         overflow = None
 703         if info.write_regs:
 704             for name, output in zip(output_names, results):
 705                 if name == 'overflow':
 706                     overflow = output
 707
 708         ov_en = yield self.dec2.e.do.oe.oe
 709         ov_ok = yield self.dec2.e.do.oe.ok
 710         print("internal overflow", overflow, ov_en, ov_ok)
 711         if ov_en & ov_ok:
 712             yield from self.handle_overflow(inputs, results, overflow)
 713
 714         rc_en = yield self.dec2.e.do.rc.data
 715         if rc_en:
 716             self.handle_comparison(results)
 717
 718         # any modified return results?
 719         if info.write_regs:
 720             for name, output in zip(output_names, results):
 721                 if name == 'overflow':  # ignore, done already (above)
 722                     continue
 723                 if isinstance(output, int):
 724                     output = SelectableInt(output, 256)
 725                 if name in ['CA', 'CA32']:
 726                     if carry_en:
 727                         print("writing %s to XER" % name, output)
 728                         self.spr['XER'][XER_bits[name]] = output.value
 729                     else:
 730                         print("NOT writing %s to XER" % name, output)
 731                 elif name in info.special_regs:
 732                     print('writing special %s' % name, output, special_sprs)
 733                     if name in special_sprs:
 734                         self.spr[name] = output
 735                     else:
 736                         self.namespace[name].eq(output)
 737                     if name == 'MSR':
 738                         print('msr written', hex(self.msr.value))
 739                 else:
 740                     regnum = yield getattr(self.decoder, name)
 741                     print('writing reg %d %s' % (regnum, str(output)))
 742                     if output.bits > 64:
 743                         output = SelectableInt(output.value, 64)
 744                     self.gpr[regnum] = output
 745
 746         print("end of call", self.namespace['CIA'], self.namespace['NIA'])
 747         # UPDATE program counter
 748         self.pc.update(self.namespace)
 749
 750
 751 def inject():
 752     """Decorator factory.
 753
 754     this decorator will "inject" variables into the function's namespace,
 755     from the *dictionary* in self.namespace.  it therefore becomes possible
 756     to make it look like a whole stack of variables which would otherwise
 757     need "self." inserted in front of them (*and* for those variables to be
 758     added to the instance) "appear" in the function.
 759
 760     "self.namespace['SI']" for example becomes accessible as just "SI" but
 761     *only* inside the function, when decorated.
 762     """
 763     def variable_injector(func):
 764         @wraps(func)
 765         def decorator(*args, **kwargs):
 766             try:
 767                 func_globals = func.__globals__  # Python 2.6+
 768             except AttributeError:
 769                 func_globals = func.func_globals  # Earlier versions.
 770
 771             context = args[0].namespace  # variables to be injected
 772             saved_values = func_globals.copy()  # Shallow copy of dict.
 773             func_globals.update(context)
 774             result = func(*args, **kwargs)
 775             print("globals after", func_globals['CIA'], func_globals['NIA'])
 776             print("args[0]", args[0].namespace['CIA'],
 777                   args[0].namespace['NIA'])
 778             args[0].namespace = func_globals
 779             #exec (func.__code__, func_globals)
 780
 781             # finally:
 782             #    func_globals = saved_values  # Undo changes.
 783
 784             return result
 785
 786         return decorator
 787
 788     return variable_injector