src/soc/decoder/isa/caller.py

   1 from functools import wraps
   2 from soc.decoder.orderedset import OrderedSet
   3 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
   4                                         selectconcat)
   5 from soc.decoder.power_enums import spr_dict, XER_bits
   6 from soc.decoder.helpers import exts
   7 from collections import namedtuple
   8 import math
   9
  10 instruction_info = namedtuple('instruction_info',
  11                               'func read_regs uninit_regs write_regs ' + \
  12                               'special_regs op_fields form asmregs')
  13
  14 special_sprs = {
  15     'LR': 8,
  16     'CTR': 9,
  17     'TAR': 815,
  18     'XER': 1,
  19     'VRSAVE': 256}
  20
  21
  22 def create_args(reglist, extra=None):
  23     args = OrderedSet()
  24     for reg in reglist:
  25         args.add(reg)
  26     args = list(args)
  27     if extra:
  28         args = [extra] + args
  29     return args
  30
  31
  32 class Mem:
  33
  34     def __init__(self, bytes_per_word=8):
  35         self.mem = {}
  36         self.bytes_per_word = bytes_per_word
  37         self.word_log2 = math.ceil(math.log2(bytes_per_word))
  38
  39     def _get_shifter_mask(self, width, remainder):
  40         shifter = ((self.bytes_per_word - width) - remainder) * \
  41             8  # bits per byte
  42         mask = (1 << (width * 8)) - 1
  43         return shifter, mask
  44
  45     # TODO: Implement ld/st of lesser width
  46     def ld(self, address, width=8):
  47         remainder = address & (self.bytes_per_word - 1)
  48         address = address >> self.word_log2
  49         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  50         if address in self.mem:
  51             val = self.mem[address]
  52         else:
  53             val = 0
  54
  55         if width != self.bytes_per_word:
  56             shifter, mask = self._get_shifter_mask(width, remainder)
  57             val = val & (mask << shifter)
  58             val >>= shifter
  59         print("Read {:x} from addr {:x}".format(val, address))
  60         return val
  61
  62     def st(self, address, value, width=8):
  63         remainder = address & (self.bytes_per_word - 1)
  64         address = address >> self.word_log2
  65         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  66         print("Writing {:x} to addr {:x}".format(value, address))
  67         if width != self.bytes_per_word:
  68             if address in self.mem:
  69                 val = self.mem[address]
  70             else:
  71                 val = 0
  72             shifter, mask = self._get_shifter_mask(width, remainder)
  73             val &= ~(mask << shifter)
  74             val |= value << shifter
  75             self.mem[address] = val
  76         else:
  77             self.mem[address] = value
  78
  79     def __call__(self, addr, sz):
  80         val = self.ld(addr.value, sz)
  81         print ("memread", addr, sz, val)
  82         return SelectableInt(val, sz*8)
  83
  84     def memassign(self, addr, sz, val):
  85         print ("memassign", addr, sz, val)
  86         self.st(addr.value, val.value, sz)
  87
  88
  89 class GPR(dict):
  90     def __init__(self, decoder, regfile):
  91         dict.__init__(self)
  92         self.sd = decoder
  93         for i in range(32):
  94             self[i] = SelectableInt(regfile[i], 64)
  95
  96     def __call__(self, ridx):
  97         return self[ridx]
  98
  99     def set_form(self, form):
 100         self.form = form
 101
 102     def getz(self, rnum):
 103         #rnum = rnum.value # only SelectableInt allowed
 104         print("GPR getzero", rnum)
 105         if rnum == 0:
 106             return SelectableInt(0, 64)
 107         return self[rnum]
 108
 109     def _get_regnum(self, attr):
 110         getform = self.sd.sigforms[self.form]
 111         rnum = getattr(getform, attr)
 112         return rnum
 113
 114     def ___getitem__(self, attr):
 115         print("GPR getitem", attr)
 116         rnum = self._get_regnum(attr)
 117         return self.regfile[rnum]
 118
 119     def dump(self):
 120         for i in range(0, len(self), 8):
 121             s = []
 122             for j in range(8):
 123                 s.append("%08x" % self[i+j].value)
 124             s = ' '.join(s)
 125             print("reg", "%2d" % i, s)
 126
 127 class PC:
 128     def __init__(self, pc_init=0):
 129         self.CIA = SelectableInt(pc_init, 64)
 130         self.NIA = self.CIA + SelectableInt(4, 64)
 131
 132     def update(self, namespace):
 133         self.CIA = namespace['NIA'].narrow(64)
 134         self.NIA = self.CIA + SelectableInt(4, 64)
 135         namespace['CIA'] = self.CIA
 136         namespace['NIA'] = self.NIA
 137
 138
 139 class SPR(dict):
 140     def __init__(self, dec2, initial_sprs={}):
 141         self.sd = dec2
 142         dict.__init__(self)
 143         self.update(initial_sprs)
 144
 145     def __getitem__(self, key):
 146         # if key in special_sprs get the special spr, otherwise return key
 147         if isinstance(key, SelectableInt):
 148             key = key.value
 149         key = special_sprs.get(key, key)
 150         if key in self:
 151             return dict.__getitem__(self, key)
 152         else:
 153             info = spr_dict[key]
 154             return SelectableInt(0, info.length)
 155
 156     def __setitem__(self, key, value):
 157         if isinstance(key, SelectableInt):
 158             key = key.value
 159         key = special_sprs.get(key, key)
 160         dict.__setitem__(self, key, value)
 161
 162     def __call__(self, ridx):
 163         return self[ridx]
 164
 165
 166
 167 class ISACaller:
 168     # decoder2 - an instance of power_decoder2
 169     # regfile - a list of initial values for the registers
 170     def __init__(self, decoder2, regfile, initial_sprs={}):
 171         self.gpr = GPR(decoder2, regfile)
 172         self.mem = Mem()
 173         self.pc = PC()
 174         self.spr = SPR(decoder2, initial_sprs)
 175         # TODO, needed here:
 176         # FPR (same as GPR except for FP nums)
 177         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 178         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 179         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 180         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 181         #         -- Done
 182         # 2.3.2 LR   (actually SPR #8) -- Done
 183         # 2.3.3 CTR  (actually SPR #9) -- Done
 184         # 2.3.4 TAR  (actually SPR #815)
 185         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 186         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 187
 188         # create CR then allow portions of it to be "selectable" (below)
 189         self._cr = SelectableInt(0, 64) # underlying reg
 190         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 191
 192         # "undefined", just set to variable-bit-width int (use exts "max")
 193         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 194
 195         self.namespace = {'GPR': self.gpr,
 196                           'MEM': self.mem,
 197                           'SPR': self.spr,
 198                           'memassign': self.memassign,
 199                           'NIA': self.pc.NIA,
 200                           'CIA': self.pc.CIA,
 201                           'CR': self.cr,
 202                           'undefined': self.undefined,
 203                           'mode_is_64bit': True,
 204                           'SO': XER_bits['SO']
 205                           }
 206
 207         # field-selectable versions of Condition Register TODO check bitranges?
 208         self.crl = []
 209         for i in range(8):
 210             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 211             _cr = FieldSelectableInt(self.cr, bits)
 212             self.crl.append(_cr)
 213             self.namespace["CR%d" % i] = _cr
 214
 215         self.decoder = decoder2.dec
 216         self.dec2 = decoder2
 217
 218     def memassign(self, ea, sz, val):
 219         self.mem.memassign(ea, sz, val)
 220
 221     def prep_namespace(self, formname, op_fields):
 222         # TODO: get field names from form in decoder*1* (not decoder2)
 223         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 224         # from spec
 225         # then "yield" fields only from op_fields rather than hard-coded
 226         # list, here.
 227         fields = self.decoder.sigforms[formname]
 228         for name in op_fields:
 229             if name == 'spr':
 230                 sig = getattr(fields, name.upper())
 231             else:
 232                 sig = getattr(fields, name)
 233             val = yield sig
 234             if name == 'BF':
 235                 self.namespace[name] = val
 236             else:
 237                 self.namespace[name] = SelectableInt(val, sig.width)
 238
 239         self.namespace['XER'] = self.spr['XER']
 240         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 241
 242     def handle_carry(self, inputs, outputs):
 243         inv_a = yield self.dec2.invert_a
 244         if inv_a:
 245             inputs[0] = ~inputs[0]
 246         assert len(outputs) >= 1
 247         output = outputs[0]
 248         gts = [(x > output) == SelectableInt(1, 1) for x in inputs]
 249         print(gts)
 250         if all(gts):
 251             return True
 252         return False
 253
 254     def handle_comparison(self, outputs):
 255         out = outputs[0]
 256         out = exts(out.value, out.bits)
 257         zero = SelectableInt(out == 0, 1)
 258         positive = SelectableInt(out > 0, 1)
 259         negative = SelectableInt(out < 0, 1)
 260         SO = SelectableInt(0, 1)
 261         cr_field = selectconcat(negative, positive, zero, SO)
 262         self.crl[0].eq(cr_field)
 263
 264
 265     def call(self, name):
 266         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 267         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 268         info = self.instrs[name]
 269         yield from self.prep_namespace(info.form, info.op_fields)
 270
 271         # preserve order of register names
 272         input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
 273         print(input_names)
 274
 275         # main registers (RT, RA ...)
 276         inputs = []
 277         for name in input_names:
 278             regnum = yield getattr(self.decoder, name)
 279             regname = "_" + name
 280             self.namespace[regname] = regnum
 281             print('reading reg %d' % regnum)
 282             inputs.append(self.gpr(regnum))
 283
 284         # "special" registers
 285         for special in info.special_regs:
 286             if special in special_sprs:
 287                 inputs.append(self.spr[special])
 288             else:
 289                 inputs.append(self.namespace[special])
 290
 291         print(inputs)
 292         results = info.func(self, *inputs)
 293         print(results)
 294
 295         carry_en = yield self.dec2.e.rc.data
 296         if carry_en:
 297             cy = self.handle_carry(inputs, results)
 298
 299             self.handle_comparison(results)
 300
 301         # any modified return results?
 302         if info.write_regs:
 303             output_names = create_args(info.write_regs)
 304             for name, output in zip(output_names, results):
 305                 if name in info.special_regs:
 306                     print('writing special %s' % name, output)
 307                     if name in special_sprs:
 308                         self.spr[name] = output
 309                     else:
 310                         self.namespace[name].eq(output)
 311                 else:
 312                     regnum = yield getattr(self.decoder, name)
 313                     print('writing reg %d %s' % (regnum, str(output)))
 314                     if output.bits > 64:
 315                         output = SelectableInt(output.value, 64)
 316                     self.gpr[regnum] = output
 317
 318         # update program counter
 319         self.pc.update(self.namespace)
 320
 321
 322 def inject():
 323     """ Decorator factory. """
 324     def variable_injector(func):
 325         @wraps(func)
 326         def decorator(*args, **kwargs):
 327             try:
 328                 func_globals = func.__globals__  # Python 2.6+
 329             except AttributeError:
 330                 func_globals = func.func_globals  # Earlier versions.
 331
 332             context = args[0].namespace
 333             saved_values = func_globals.copy()  # Shallow copy of dict.
 334             func_globals.update(context)
 335             result = func(*args, **kwargs)
 336             args[0].namespace = func_globals
 337             #exec (func.__code__, func_globals)
 338
 339             #finally:
 340             #    func_globals = saved_values  # Undo changes.
 341
 342             return result
 343
 344         return decorator
 345
 346     return variable_injector
 347