src/soc/decoder/isa/caller.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020 Michael Nolan
   4 # Funded by NLnet http://nlnet.nl
   5 """core of the python-based POWER9 simulator
   6
   7 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   8 not speed, it is for both learning and educational purposes, as well as
   9 a method of verifying the HDL.
  10
  11 related bugs:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
  14 """
  15
  16 from nmigen.back.pysim import Settle
  17 from functools import wraps
  18 from copy import copy
  19 from soc.decoder.orderedset import OrderedSet
  20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  21                                         selectconcat)
  22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
  23                                      insns, MicrOp, In1Sel, In2Sel, In3Sel,
  24                                      OutSel)
  25 from soc.decoder.helpers import exts, gtu, ltu, undefined
  26 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
  27 from soc.decoder.power_svp64 import SVP64RM, decode_extra
  28
  29 from collections import namedtuple
  30 import math
  31 import sys
  32
  33 instruction_info = namedtuple('instruction_info',
  34                               'func read_regs uninit_regs write_regs ' +
  35                               'special_regs op_fields form asmregs')
  36
  37 special_sprs = {
  38     'LR': 8,
  39     'CTR': 9,
  40     'TAR': 815,
  41     'XER': 1,
  42     'VRSAVE': 256}
  43
  44
  45 def swap_order(x, nbytes):
  46     x = x.to_bytes(nbytes, byteorder='little')
  47     x = int.from_bytes(x, byteorder='big', signed=False)
  48     return x
  49
  50
  51 REG_SORT_ORDER = {
  52     # TODO (lkcl): adjust other registers that should be in a particular order
  53     # probably CA, CA32, and CR
  54     "RT": 0,
  55     "RA": 0,
  56     "RB": 0,
  57     "RS": 0,
  58     "CR": 0,
  59     "LR": 0,
  60     "CTR": 0,
  61     "TAR": 0,
  62     "CA": 0,
  63     "CA32": 0,
  64     "MSR": 0,
  65
  66     "overflow": 1,
  67 }
  68
  69
  70 def create_args(reglist, extra=None):
  71     retval = list(OrderedSet(reglist))
  72     retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
  73     if extra is not None:
  74         return [extra] + retval
  75     return retval
  76
  77
  78 class Mem:
  79
  80     def __init__(self, row_bytes=8, initial_mem=None):
  81         self.mem = {}
  82         self.bytes_per_word = row_bytes
  83         self.word_log2 = math.ceil(math.log2(row_bytes))
  84         print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
  85         if not initial_mem:
  86             return
  87
  88         # different types of memory data structures recognised (for convenience)
  89         if isinstance(initial_mem, list):
  90             initial_mem = (0, initial_mem)
  91         if isinstance(initial_mem, tuple):
  92             startaddr, mem = initial_mem
  93             initial_mem = {}
  94             for i, val in enumerate(mem):
  95                 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
  96
  97         for addr, (val, width) in initial_mem.items():
  98             #val = swap_order(val, width)
  99             self.st(addr, val, width, swap=False)
 100
 101     def _get_shifter_mask(self, wid, remainder):
 102         shifter = ((self.bytes_per_word - wid) - remainder) * \
 103             8  # bits per byte
 104         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
 105         # BE/LE mode?
 106         shifter = remainder * 8
 107         mask = (1 << (wid * 8)) - 1
 108         print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
 109         return shifter, mask
 110
 111     # TODO: Implement ld/st of lesser width
 112     def ld(self, address, width=8, swap=True, check_in_mem=False):
 113         print("ld from addr 0x{:x} width {:d}".format(address, width))
 114         remainder = address & (self.bytes_per_word - 1)
 115         address = address >> self.word_log2
 116         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 117         if address in self.mem:
 118             val = self.mem[address]
 119         elif check_in_mem:
 120             return None
 121         else:
 122             val = 0
 123         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
 124
 125         if width != self.bytes_per_word:
 126             shifter, mask = self._get_shifter_mask(width, remainder)
 127             print("masking", hex(val), hex(mask << shifter), shifter)
 128             val = val & (mask << shifter)
 129             val >>= shifter
 130         if swap:
 131             val = swap_order(val, width)
 132         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
 133         return val
 134
 135     def st(self, addr, v, width=8, swap=True):
 136         staddr = addr
 137         remainder = addr & (self.bytes_per_word - 1)
 138         addr = addr >> self.word_log2
 139         print("Writing 0x{:x} to ST 0x{:x} "
 140               "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
 141         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 142         if swap:
 143             v = swap_order(v, width)
 144         if width != self.bytes_per_word:
 145             if addr in self.mem:
 146                 val = self.mem[addr]
 147             else:
 148                 val = 0
 149             shifter, mask = self._get_shifter_mask(width, remainder)
 150             val &= ~(mask << shifter)
 151             val |= v << shifter
 152             self.mem[addr] = val
 153         else:
 154             self.mem[addr] = v
 155         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 156
 157     def __call__(self, addr, sz):
 158         val = self.ld(addr.value, sz, swap=False)
 159         print("memread", addr, sz, val)
 160         return SelectableInt(val, sz*8)
 161
 162     def memassign(self, addr, sz, val):
 163         print("memassign", addr, sz, val)
 164         self.st(addr.value, val.value, sz, swap=False)
 165
 166
 167 class GPR(dict):
 168     def __init__(self, decoder, isacaller, svstate, regfile):
 169         dict.__init__(self)
 170         self.sd = decoder
 171         self.isacaller = isacaller
 172         self.svstate = svstate
 173         for i in range(32):
 174             self[i] = SelectableInt(regfile[i], 64)
 175
 176     def __call__(self, ridx):
 177         return self[ridx]
 178
 179     def set_form(self, form):
 180         self.form = form
 181
 182     def getz(self, rnum):
 183         # rnum = rnum.value # only SelectableInt allowed
 184         print("GPR getzero", rnum)
 185         if rnum == 0:
 186             return SelectableInt(0, 64)
 187         return self[rnum]
 188
 189     def _get_regnum(self, attr):
 190         getform = self.sd.sigforms[self.form]
 191         rnum = getattr(getform, attr)
 192         return rnum
 193
 194     def ___getitem__(self, attr):
 195         """ XXX currently not used
 196         """
 197         rnum = self._get_regnum(attr)
 198         offs = self.svstate.srcstep
 199         print("GPR getitem", attr, rnum, "srcoffs", offs)
 200         return self.regfile[rnum]
 201
 202     def dump(self):
 203         for i in range(0, len(self), 8):
 204             s = []
 205             for j in range(8):
 206                 s.append("%08x" % self[i+j].value)
 207             s = ' '.join(s)
 208             print("reg", "%2d" % i, s)
 209
 210
 211 class PC:
 212     def __init__(self, pc_init=0):
 213         self.CIA = SelectableInt(pc_init, 64)
 214         self.NIA = self.CIA + SelectableInt(4, 64)
 215
 216     def update(self, namespace):
 217         self.CIA = namespace['NIA'].narrow(64)
 218         self.NIA = self.CIA + SelectableInt(4, 64)
 219         namespace['CIA'] = self.CIA
 220         namespace['NIA'] = self.NIA
 221
 222
 223 # Simple-V: see https://libre-soc.org/openpower/sv
 224 class SVP64State:
 225     def __init__(self, init=0):
 226         self.spr = SelectableInt(init, 32)
 227         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
 228         self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
 229         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
 230         self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
 231         self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
 232         self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
 233         self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
 234
 235
 236 # SVP64 ReMap field
 237 class SVP64RMFields:
 238     def __init__(self, init=0):
 239         self.spr = SelectableInt(init, 24)
 240         # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
 241         self.mmode = FieldSelectableInt(self.spr, [0])
 242         self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
 243         self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
 244         self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
 245         self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
 246         self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
 247         self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
 248
 249
 250 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
 251 class SVP64PrefixFields:
 252     def __init__(self):
 253         self.insn = SelectableInt(0, 32)
 254         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
 255         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
 256         self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
 257         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
 258         self.rm = FieldSelectableInt(self.insn, rmfields)
 259
 260
 261 class SPR(dict):
 262     def __init__(self, dec2, initial_sprs={}):
 263         self.sd = dec2
 264         dict.__init__(self)
 265         for key, v in initial_sprs.items():
 266             if isinstance(key, SelectableInt):
 267                 key = key.value
 268             key = special_sprs.get(key, key)
 269             if isinstance(key, int):
 270                 info = spr_dict[key]
 271             else:
 272                 info = spr_byname[key]
 273             if not isinstance(v, SelectableInt):
 274                 v = SelectableInt(v, info.length)
 275             self[key] = v
 276
 277     def __getitem__(self, key):
 278         print("get spr", key)
 279         print("dict", self.items())
 280         # if key in special_sprs get the special spr, otherwise return key
 281         if isinstance(key, SelectableInt):
 282             key = key.value
 283         if isinstance(key, int):
 284             key = spr_dict[key].SPR
 285         key = special_sprs.get(key, key)
 286         if key == 'HSRR0':  # HACK!
 287             key = 'SRR0'
 288         if key == 'HSRR1':  # HACK!
 289             key = 'SRR1'
 290         if key in self:
 291             res = dict.__getitem__(self, key)
 292         else:
 293             if isinstance(key, int):
 294                 info = spr_dict[key]
 295             else:
 296                 info = spr_byname[key]
 297             dict.__setitem__(self, key, SelectableInt(0, info.length))
 298             res = dict.__getitem__(self, key)
 299         print("spr returning", key, res)
 300         return res
 301
 302     def __setitem__(self, key, value):
 303         if isinstance(key, SelectableInt):
 304             key = key.value
 305         if isinstance(key, int):
 306             key = spr_dict[key].SPR
 307             print("spr key", key)
 308         key = special_sprs.get(key, key)
 309         if key == 'HSRR0':  # HACK!
 310             self.__setitem__('SRR0', value)
 311         if key == 'HSRR1':  # HACK!
 312             self.__setitem__('SRR1', value)
 313         print("setting spr", key, value)
 314         dict.__setitem__(self, key, value)
 315
 316     def __call__(self, ridx):
 317         return self[ridx]
 318
 319 def get_pdecode_idx_in(dec2, name):
 320     op = dec2.dec.op
 321     in1_sel = yield op.in1_sel
 322     in2_sel = yield op.in2_sel
 323     in3_sel = yield op.in3_sel
 324     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 325     in1 = yield dec2.e.read_reg1.data
 326     in2 = yield dec2.e.read_reg2.data
 327     in3 = yield dec2.e.read_reg3.data
 328     in1_isvec = yield dec2.in1_isvec
 329     in2_isvec = yield dec2.in2_isvec
 330     in3_isvec = yield dec2.in3_isvec
 331     print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
 332     # identify which regnames map to in1/2/3
 333     if name == 'RA':
 334         if (in1_sel == In1Sel.RA.value or
 335             (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
 336             return in1, in1_isvec
 337         if in1_sel == In1Sel.RA_OR_ZERO.value:
 338             return in1, in1_isvec
 339     elif name == 'RB':
 340         if in2_sel == In2Sel.RB.value:
 341             return in2, in2_isvec
 342         if in3_sel == In3Sel.RB.value:
 343             return in3, in3_isvec
 344     # XXX TODO, RC doesn't exist yet!
 345     elif name == 'RC':
 346         assert False, "RC does not exist yet"
 347     elif name == 'RS':
 348         if in1_sel == In1Sel.RS.value:
 349             return in1, in1_isvec
 350         if in2_sel == In2Sel.RS.value:
 351             return in2, in2_isvec
 352         if in3_sel == In3Sel.RS.value:
 353             return in3, in3_isvec
 354     return None, False
 355
 356
 357 def get_pdecode_idx_out(dec2, name):
 358     op = dec2.dec.op
 359     out_sel = yield op.out_sel
 360     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 361     out = yield dec2.e.write_reg.data
 362     o_isvec = yield dec2.o_isvec
 363     print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
 364     # identify which regnames map to out / o2
 365     if name == 'RA':
 366         if out_sel == OutSel.RA.value:
 367             return out, o_isvec
 368     elif name == 'RT':
 369         if out_sel == OutSel.RT.value:
 370             return out, o_isvec
 371     print ("get_pdecode_idx_out not found", name)
 372     return None, False
 373
 374
 375 # XXX TODO
 376 def get_pdecode_idx_out2(dec2, name):
 377     op = dec2.dec.op
 378     print ("TODO: get_pdecode_idx_out2", name)
 379     return None, False
 380
 381
 382 class ISACaller:
 383     # decoder2 - an instance of power_decoder2
 384     # regfile - a list of initial values for the registers
 385     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 386     # respect_pc - tracks the program counter.  requires initial_insns
 387     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 388                  initial_mem=None, initial_msr=0,
 389                  initial_svstate=0,
 390                  initial_insns=None, respect_pc=False,
 391                  disassembly=None,
 392                  initial_pc=0,
 393                  bigendian=False):
 394
 395         self.bigendian = bigendian
 396         self.halted = False
 397         self.is_svp64_mode = False
 398         self.respect_pc = respect_pc
 399         if initial_sprs is None:
 400             initial_sprs = {}
 401         if initial_mem is None:
 402             initial_mem = {}
 403         if initial_insns is None:
 404             initial_insns = {}
 405             assert self.respect_pc == False, "instructions required to honor pc"
 406
 407         print("ISACaller insns", respect_pc, initial_insns, disassembly)
 408         print("ISACaller initial_msr", initial_msr)
 409
 410         # "fake program counter" mode (for unit testing)
 411         self.fake_pc = 0
 412         disasm_start = 0
 413         if not respect_pc:
 414             if isinstance(initial_mem, tuple):
 415                 self.fake_pc = initial_mem[0]
 416                 disasm_start = self.fake_pc
 417         else:
 418             disasm_start = initial_pc
 419
 420         # disassembly: we need this for now (not given from the decoder)
 421         self.disassembly = {}
 422         if disassembly:
 423             for i, code in enumerate(disassembly):
 424                 self.disassembly[i*4 + disasm_start] = code
 425
 426         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 427         self.svp64rm = SVP64RM()
 428         self.svstate = SVP64State(initial_svstate)
 429         self.gpr = GPR(decoder2, self, self.svstate, regfile)
 430         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 431         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 432         self.pc = PC()
 433         self.spr = SPR(decoder2, initial_sprs)
 434         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 435
 436         # TODO, needed here:
 437         # FPR (same as GPR except for FP nums)
 438         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 439         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 440         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 441         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 442         #         -- Done
 443         # 2.3.2 LR   (actually SPR #8) -- Done
 444         # 2.3.3 CTR  (actually SPR #9) -- Done
 445         # 2.3.4 TAR  (actually SPR #815)
 446         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 447         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 448
 449         # create CR then allow portions of it to be "selectable" (below)
 450         #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
 451         self.cr = SelectableInt(initial_cr, 64)  # underlying reg
 452         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 453
 454         # "undefined", just set to variable-bit-width int (use exts "max")
 455         #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 456
 457         self.namespace = {}
 458         self.namespace.update(self.spr)
 459         self.namespace.update({'GPR': self.gpr,
 460                                'MEM': self.mem,
 461                                'SPR': self.spr,
 462                                'memassign': self.memassign,
 463                                'NIA': self.pc.NIA,
 464                                'CIA': self.pc.CIA,
 465                                'CR': self.cr,
 466                                'MSR': self.msr,
 467                                'undefined': undefined,
 468                                'mode_is_64bit': True,
 469                                'SO': XER_bits['SO']
 470                                })
 471
 472         # update pc to requested start point
 473         self.set_pc(initial_pc)
 474
 475         # field-selectable versions of Condition Register TODO check bitranges?
 476         self.crl = []
 477         for i in range(8):
 478             bits = tuple(range(i*4+32, (i+1)*4+32))  # errr... maybe?
 479             _cr = FieldSelectableInt(self.cr, bits)
 480             self.crl.append(_cr)
 481             self.namespace["CR%d" % i] = _cr
 482
 483         self.decoder = decoder2.dec
 484         self.dec2 = decoder2
 485
 486     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
 487         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
 488         # store CIA(+4?) in SRR0, set NIA to 0x700
 489         # store MSR in SRR1, set MSR to um errr something, have to check spec
 490         self.spr['SRR0'].value = self.pc.CIA.value
 491         self.spr['SRR1'].value = self.namespace['MSR'].value
 492         self.trap_nia = SelectableInt(trap_addr, 64)
 493         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 494
 495         # set exception bits.  TODO: this should, based on the address
 496         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
 497         # bits appropriately.  however it turns out that *for now* in all
 498         # cases (all trap_addrs) the exact same thing is needed.
 499         self.msr[MSRb.IR] = 0
 500         self.msr[MSRb.DR] = 0
 501         self.msr[MSRb.FE0] = 0
 502         self.msr[MSRb.FE1] = 0
 503         self.msr[MSRb.EE] = 0
 504         self.msr[MSRb.RI] = 0
 505         self.msr[MSRb.SF] = 1
 506         self.msr[MSRb.TM] = 0
 507         self.msr[MSRb.VEC] = 0
 508         self.msr[MSRb.VSX] = 0
 509         self.msr[MSRb.PR] = 0
 510         self.msr[MSRb.FP] = 0
 511         self.msr[MSRb.PMM] = 0
 512         self.msr[MSRb.TEs] = 0
 513         self.msr[MSRb.TEe] = 0
 514         self.msr[MSRb.UND] = 0
 515         self.msr[MSRb.LE] = 1
 516
 517     def memassign(self, ea, sz, val):
 518         self.mem.memassign(ea, sz, val)
 519
 520     def prep_namespace(self, formname, op_fields):
 521         # TODO: get field names from form in decoder*1* (not decoder2)
 522         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 523         # from spec
 524         # then "yield" fields only from op_fields rather than hard-coded
 525         # list, here.
 526         fields = self.decoder.sigforms[formname]
 527         for name in op_fields:
 528             if name == 'spr':
 529                 sig = getattr(fields, name.upper())
 530             else:
 531                 sig = getattr(fields, name)
 532             val = yield sig
 533             # these are all opcode fields involved in index-selection of CR,
 534             # and need to do "standard" arithmetic.  CR[BA+32] for example
 535             # would, if using SelectableInt, only be 5-bit.
 536             if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
 537                 self.namespace[name] = val
 538             else:
 539                 self.namespace[name] = SelectableInt(val, sig.width)
 540
 541         self.namespace['XER'] = self.spr['XER']
 542         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 543         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 544
 545     def handle_carry_(self, inputs, outputs, already_done):
 546         inv_a = yield self.dec2.e.do.invert_in
 547         if inv_a:
 548             inputs[0] = ~inputs[0]
 549
 550         imm_ok = yield self.dec2.e.do.imm_data.ok
 551         if imm_ok:
 552             imm = yield self.dec2.e.do.imm_data.data
 553             inputs.append(SelectableInt(imm, 64))
 554         assert len(outputs) >= 1
 555         print("outputs", repr(outputs))
 556         if isinstance(outputs, list) or isinstance(outputs, tuple):
 557             output = outputs[0]
 558         else:
 559             output = outputs
 560         gts = []
 561         for x in inputs:
 562             print("gt input", x, output)
 563             gt = (gtu(x, output))
 564             gts.append(gt)
 565         print(gts)
 566         cy = 1 if any(gts) else 0
 567         print("CA", cy, gts)
 568         if not (1 & already_done):
 569             self.spr['XER'][XER_bits['CA']] = cy
 570
 571         print("inputs", already_done, inputs)
 572         # 32 bit carry
 573         # ARGH... different for OP_ADD... *sigh*...
 574         op = yield self.dec2.e.do.insn_type
 575         if op == MicrOp.OP_ADD.value:
 576             res32 = (output.value & (1 << 32)) != 0
 577             a32 = (inputs[0].value & (1 << 32)) != 0
 578             if len(inputs) >= 2:
 579                 b32 = (inputs[1].value & (1 << 32)) != 0
 580             else:
 581                 b32 = False
 582             cy32 = res32 ^ a32 ^ b32
 583             print("CA32 ADD", cy32)
 584         else:
 585             gts = []
 586             for x in inputs:
 587                 print("input", x, output)
 588                 print("     x[32:64]", x, x[32:64])
 589                 print("     o[32:64]", output, output[32:64])
 590                 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
 591                 gts.append(gt)
 592             cy32 = 1 if any(gts) else 0
 593             print("CA32", cy32, gts)
 594         if not (2 & already_done):
 595             self.spr['XER'][XER_bits['CA32']] = cy32
 596
 597     def handle_overflow(self, inputs, outputs, div_overflow):
 598         if hasattr(self.dec2.e.do, "invert_in"):
 599             inv_a = yield self.dec2.e.do.invert_in
 600             if inv_a:
 601                 inputs[0] = ~inputs[0]
 602
 603         imm_ok = yield self.dec2.e.do.imm_data.ok
 604         if imm_ok:
 605             imm = yield self.dec2.e.do.imm_data.data
 606             inputs.append(SelectableInt(imm, 64))
 607         assert len(outputs) >= 1
 608         print("handle_overflow", inputs, outputs, div_overflow)
 609         if len(inputs) < 2 and div_overflow is None:
 610             return
 611
 612         # div overflow is different: it's returned by the pseudo-code
 613         # because it's more complex than can be done by analysing the output
 614         if div_overflow is not None:
 615             ov, ov32 = div_overflow, div_overflow
 616         # arithmetic overflow can be done by analysing the input and output
 617         elif len(inputs) >= 2:
 618             output = outputs[0]
 619
 620             # OV (64-bit)
 621             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 622             output_sgn = exts(output.value, output.bits) < 0
 623             ov = 1 if input_sgn[0] == input_sgn[1] and \
 624                 output_sgn != input_sgn[0] else 0
 625
 626             # OV (32-bit)
 627             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 628             output32_sgn = exts(output.value, 32) < 0
 629             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 630                 output32_sgn != input32_sgn[0] else 0
 631
 632         self.spr['XER'][XER_bits['OV']] = ov
 633         self.spr['XER'][XER_bits['OV32']] = ov32
 634         so = self.spr['XER'][XER_bits['SO']]
 635         so = so | ov
 636         self.spr['XER'][XER_bits['SO']] = so
 637
 638     def handle_comparison(self, outputs):
 639         out = outputs[0]
 640         assert isinstance(out, SelectableInt), \
 641             "out zero not a SelectableInt %s" % repr(outputs)
 642         print("handle_comparison", out.bits, hex(out.value))
 643         # TODO - XXX *processor* in 32-bit mode
 644         # https://bugs.libre-soc.org/show_bug.cgi?id=424
 645         # if is_32bit:
 646         #    o32 = exts(out.value, 32)
 647         #    print ("handle_comparison exts 32 bit", hex(o32))
 648         out = exts(out.value, out.bits)
 649         print("handle_comparison exts", hex(out))
 650         zero = SelectableInt(out == 0, 1)
 651         positive = SelectableInt(out > 0, 1)
 652         negative = SelectableInt(out < 0, 1)
 653         SO = self.spr['XER'][XER_bits['SO']]
 654         print("handle_comparison SO", SO)
 655         cr_field = selectconcat(negative, positive, zero, SO)
 656         self.crl[0].eq(cr_field)
 657
 658     def set_pc(self, pc_val):
 659         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 660         self.pc.update(self.namespace)
 661
 662     def setup_one(self):
 663         """set up one instruction
 664         """
 665         if self.respect_pc:
 666             pc = self.pc.CIA.value
 667         else:
 668             pc = self.fake_pc
 669         self._pc = pc
 670         ins = self.imem.ld(pc, 4, False, True)
 671         if ins is None:
 672             raise KeyError("no instruction at 0x%x" % pc)
 673         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 674         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 675
 676         yield self.dec2.sv_rm.eq(0)
 677         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 678         yield self.dec2.dec.bigendian.eq(self.bigendian)
 679         yield self.dec2.state.msr.eq(self.msr.value)
 680         yield self.dec2.state.pc.eq(pc)
 681
 682         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
 683         yield Settle()
 684         opcode = yield self.dec2.dec.opcode_in
 685         pfx = SVP64PrefixFields()
 686         pfx.insn.value = opcode
 687         major = pfx.major.asint(msb0=True) # MSB0 inversion
 688         print ("prefix test: opcode:", major, bin(major),
 689                 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
 690         self.is_svp64_mode = ((major == 0b000001) and
 691                               pfx.insn[7].value == 0b1 and
 692                               pfx.insn[9].value == 0b1)
 693         if not self.is_svp64_mode:
 694             return
 695
 696         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
 697         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
 698         sv_rm = pfx.rm.asint()
 699         ins = self.imem.ld(pc+4, 4, False, True)
 700         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
 701         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
 702         yield self.dec2.sv_rm.eq(sv_rm)                        # svp64 prefix
 703         yield Settle()
 704
 705     def execute_one(self):
 706         """execute one instruction
 707         """
 708         # get the disassembly code for this instruction
 709         if self.is_svp64_mode:
 710             code = self.disassembly[self._pc+4]
 711             print("    svp64 sim-execute", hex(self._pc), code)
 712         else:
 713             code = self.disassembly[self._pc]
 714             print("sim-execute", hex(self._pc), code)
 715         opname = code.split(' ')[0]
 716         yield from self.call(opname)
 717
 718         if not self.respect_pc:
 719             self.fake_pc += 4
 720         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 721
 722     def get_assembly_name(self):
 723         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 724         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 725         dec_insn = yield self.dec2.e.do.insn
 726         asmcode = yield self.dec2.dec.op.asmcode
 727         print("get assembly name asmcode", asmcode, hex(dec_insn))
 728         asmop = insns.get(asmcode, None)
 729         int_op = yield self.dec2.dec.op.internal_op
 730
 731         # sigh reconstruct the assembly instruction name
 732         if hasattr(self.dec2.e.do, "oe"):
 733             ov_en = yield self.dec2.e.do.oe.oe
 734             ov_ok = yield self.dec2.e.do.oe.ok
 735         else:
 736             ov_en = False
 737             ov_ok = False
 738         if hasattr(self.dec2.e.do, "rc"):
 739             rc_en = yield self.dec2.e.do.rc.rc
 740             rc_ok = yield self.dec2.e.do.rc.ok
 741         else:
 742             rc_en = False
 743             rc_ok = False
 744         # grrrr have to special-case MUL op (see DecodeOE)
 745         print("ov %d en %d rc %d en %d op %d" %
 746               (ov_ok, ov_en, rc_ok, rc_en, int_op))
 747         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
 748             print("mul op")
 749             if rc_en & rc_ok:
 750                 asmop += "."
 751         else:
 752             if not asmop.endswith("."):  # don't add "." to "andis."
 753                 if rc_en & rc_ok:
 754                     asmop += "."
 755         if hasattr(self.dec2.e.do, "lk"):
 756             lk = yield self.dec2.e.do.lk
 757             if lk:
 758                 asmop += "l"
 759         print("int_op", int_op)
 760         if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
 761             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 762             print("AA", AA)
 763             if AA:
 764                 asmop += "a"
 765         spr_msb = yield from self.get_spr_msb()
 766         if int_op == MicrOp.OP_MFCR.value:
 767             if spr_msb:
 768                 asmop = 'mfocrf'
 769             else:
 770                 asmop = 'mfcr'
 771         # XXX TODO: for whatever weird reason this doesn't work
 772         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 773         if int_op == MicrOp.OP_MTCRF.value:
 774             if spr_msb:
 775                 asmop = 'mtocrf'
 776             else:
 777                 asmop = 'mtcrf'
 778         return asmop
 779
 780     def get_spr_msb(self):
 781         dec_insn = yield self.dec2.e.do.insn
 782         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 783
 784     def call(self, name):
 785         """call(opcode) - the primary execution point for instructions
 786         """
 787         name = name.strip()  # remove spaces if not already done so
 788         if self.halted:
 789             print("halted - not executing", name)
 790             return
 791
 792         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 793         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 794         asmop = yield from self.get_assembly_name()
 795         print("call", name, asmop)
 796
 797         # check privileged
 798         int_op = yield self.dec2.dec.op.internal_op
 799         spr_msb = yield from self.get_spr_msb()
 800
 801         instr_is_privileged = False
 802         if int_op in [MicrOp.OP_ATTN.value,
 803                       MicrOp.OP_MFMSR.value,
 804                       MicrOp.OP_MTMSR.value,
 805                       MicrOp.OP_MTMSRD.value,
 806                       # TODO: OP_TLBIE
 807                       MicrOp.OP_RFID.value]:
 808             instr_is_privileged = True
 809         if int_op in [MicrOp.OP_MFSPR.value,
 810                       MicrOp.OP_MTSPR.value] and spr_msb:
 811             instr_is_privileged = True
 812
 813         print("is priv", instr_is_privileged, hex(self.msr.value),
 814               self.msr[MSRb.PR])
 815         # check MSR priv bit and whether op is privileged: if so, throw trap
 816         if instr_is_privileged and self.msr[MSRb.PR] == 1:
 817             self.TRAP(0x700, PIb.PRIV)
 818             self.namespace['NIA'] = self.trap_nia
 819             self.pc.update(self.namespace)
 820             return
 821
 822         # check halted condition
 823         if name == 'attn':
 824             self.halted = True
 825             return
 826
 827         # check illegal instruction
 828         illegal = False
 829         if name not in ['mtcrf', 'mtocrf']:
 830             illegal = name != asmop
 831
 832         if illegal:
 833             print("illegal", name, asmop)
 834             self.TRAP(0x700, PIb.ILLEG)
 835             self.namespace['NIA'] = self.trap_nia
 836             self.pc.update(self.namespace)
 837             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
 838                   (name, asmop, self.pc.CIA.value))
 839             return
 840
 841         info = self.instrs[name]
 842         yield from self.prep_namespace(info.form, info.op_fields)
 843
 844         # preserve order of register names
 845         input_names = create_args(list(info.read_regs) +
 846                                   list(info.uninit_regs))
 847         print(input_names)
 848
 849         # get SVP64 entry for the current instruction
 850         sv_rm = self.svp64rm.instrs.get(name)
 851         if sv_rm is not None:
 852             dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
 853         else:
 854             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
 855         print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 856
 857         # main input registers (RT, RA ...)
 858         inputs = []
 859         for name in input_names:
 860             # using PowerDecoder2, first, find the decoder index.
 861             # (mapping name RA RB RC RS to in1, in2, in3)
 862             regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
 863             if regnum is None:
 864                 # doing this is not part of svp64, it's because output
 865                 # registers, to be modified, need to be in the namespace.
 866                 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
 867             # in case getting the register number is needed, _RA, _RB
 868             regname = "_" + name
 869             self.namespace[regname] = regnum
 870             print('reading reg %s %d' % (name, regnum), is_vec)
 871             reg_val = self.gpr(regnum)
 872             inputs.append(reg_val)
 873
 874         # "special" registers
 875         for special in info.special_regs:
 876             if special in special_sprs:
 877                 inputs.append(self.spr[special])
 878             else:
 879                 inputs.append(self.namespace[special])
 880
 881         # clear trap (trap) NIA
 882         self.trap_nia = None
 883
 884         print(inputs)
 885         results = info.func(self, *inputs)
 886         print(results)
 887
 888         # "inject" decorator takes namespace from function locals: we need to
 889         # overwrite NIA being overwritten (sigh)
 890         if self.trap_nia is not None:
 891             self.namespace['NIA'] = self.trap_nia
 892
 893         print("after func", self.namespace['CIA'], self.namespace['NIA'])
 894
 895         # detect if CA/CA32 already in outputs (sra*, basically)
 896         already_done = 0
 897         if info.write_regs:
 898             output_names = create_args(info.write_regs)
 899             for name in output_names:
 900                 if name == 'CA':
 901                     already_done |= 1
 902                 if name == 'CA32':
 903                     already_done |= 2
 904
 905         print("carry already done?", bin(already_done))
 906         if hasattr(self.dec2.e.do, "output_carry"):
 907             carry_en = yield self.dec2.e.do.output_carry
 908         else:
 909             carry_en = False
 910         if carry_en:
 911             yield from self.handle_carry_(inputs, results, already_done)
 912
 913         # detect if overflow was in return result
 914         overflow = None
 915         if info.write_regs:
 916             for name, output in zip(output_names, results):
 917                 if name == 'overflow':
 918                     overflow = output
 919
 920         if hasattr(self.dec2.e.do, "oe"):
 921             ov_en = yield self.dec2.e.do.oe.oe
 922             ov_ok = yield self.dec2.e.do.oe.ok
 923         else:
 924             ov_en = False
 925             ov_ok = False
 926         print("internal overflow", overflow, ov_en, ov_ok)
 927         if ov_en & ov_ok:
 928             yield from self.handle_overflow(inputs, results, overflow)
 929
 930         if hasattr(self.dec2.e.do, "rc"):
 931             rc_en = yield self.dec2.e.do.rc.rc
 932         else:
 933             rc_en = False
 934         if rc_en:
 935             self.handle_comparison(results)
 936
 937         # any modified return results?
 938         if info.write_regs:
 939             for name, output in zip(output_names, results):
 940                 if name == 'overflow':  # ignore, done already (above)
 941                     continue
 942                 if isinstance(output, int):
 943                     output = SelectableInt(output, 256)
 944                 if name in ['CA', 'CA32']:
 945                     if carry_en:
 946                         print("writing %s to XER" % name, output)
 947                         self.spr['XER'][XER_bits[name]] = output.value
 948                     else:
 949                         print("NOT writing %s to XER" % name, output)
 950                 elif name in info.special_regs:
 951                     print('writing special %s' % name, output, special_sprs)
 952                     if name in special_sprs:
 953                         self.spr[name] = output
 954                     else:
 955                         self.namespace[name].eq(output)
 956                     if name == 'MSR':
 957                         print('msr written', hex(self.msr.value))
 958                 else:
 959                     regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
 960                                                 name)
 961                     if regnum is None:
 962                         # temporary hack for not having 2nd output
 963                         regnum = yield getattr(self.decoder, name)
 964                         is_vec = False
 965                     print('writing reg %d %s' % (regnum, str(output)), is_vec)
 966                     if output.bits > 64:
 967                         output = SelectableInt(output.value, 64)
 968                     self.gpr[regnum] = output
 969
 970         print("end of call", self.namespace['CIA'], self.namespace['NIA'])
 971         # UPDATE program counter
 972         self.pc.update(self.namespace)
 973
 974
 975 def inject():
 976     """Decorator factory.
 977
 978     this decorator will "inject" variables into the function's namespace,
 979     from the *dictionary* in self.namespace.  it therefore becomes possible
 980     to make it look like a whole stack of variables which would otherwise
 981     need "self." inserted in front of them (*and* for those variables to be
 982     added to the instance) "appear" in the function.
 983
 984     "self.namespace['SI']" for example becomes accessible as just "SI" but
 985     *only* inside the function, when decorated.
 986     """
 987     def variable_injector(func):
 988         @wraps(func)
 989         def decorator(*args, **kwargs):
 990             try:
 991                 func_globals = func.__globals__  # Python 2.6+
 992             except AttributeError:
 993                 func_globals = func.func_globals  # Earlier versions.
 994
 995             context = args[0].namespace  # variables to be injected
 996             saved_values = func_globals.copy()  # Shallow copy of dict.
 997             func_globals.update(context)
 998             result = func(*args, **kwargs)
 999             print("globals after", func_globals['CIA'], func_globals['NIA'])
1000             print("args[0]", args[0].namespace['CIA'],
1001                   args[0].namespace['NIA'])
1002             args[0].namespace = func_globals
1003             #exec (func.__code__, func_globals)
1004
1005             # finally:
1006             #    func_globals = saved_values  # Undo changes.
1007
1008             return result
1009
1010         return decorator
1011
1012     return variable_injector