src/soc/decoder/isa/caller.py

   1 """core of the python-based POWER9 simulator
   2
   3 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   4 not speed, it is for both learning and educational purposes, as well as
   5 a method of verifying the HDL.
   6 """
   7
   8 from functools import wraps
   9 from soc.decoder.orderedset import OrderedSet
  10 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  11                                         selectconcat)
  12 from soc.decoder.power_enums import spr_dict, XER_bits, insns, InternalOp
  13 from soc.decoder.helpers import exts
  14 from collections import namedtuple
  15 import math
  16 import sys
  17
  18 instruction_info = namedtuple('instruction_info',
  19                               'func read_regs uninit_regs write_regs ' + \
  20                               'special_regs op_fields form asmregs')
  21
  22 special_sprs = {
  23     'LR': 8,
  24     'CTR': 9,
  25     'TAR': 815,
  26     'XER': 1,
  27     'VRSAVE': 256}
  28
  29
  30 def swap_order(x, nbytes):
  31     x = x.to_bytes(nbytes, byteorder='little')
  32     x = int.from_bytes(x, byteorder='big', signed=False)
  33     return x
  34
  35
  36 def create_args(reglist, extra=None):
  37     args = OrderedSet()
  38     for reg in reglist:
  39         args.add(reg)
  40     args = list(args)
  41     if extra:
  42         args = [extra] + args
  43     return args
  44
  45
  46 class Mem:
  47
  48     def __init__(self, row_bytes=8, initial_mem=None):
  49         self.mem = {}
  50         self.bytes_per_word = row_bytes
  51         self.word_log2 = math.ceil(math.log2(row_bytes))
  52         print ("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
  53         if not initial_mem:
  54             return
  55
  56         # different types of memory data structures recognised (for convenience)
  57         if isinstance(initial_mem, list):
  58             initial_mem = (0, initial_mem)
  59         if isinstance(initial_mem, tuple):
  60             startaddr, mem = initial_mem
  61             initial_mem = {}
  62             for i, val in enumerate(mem):
  63                 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
  64
  65         for addr, (val, width) in initial_mem.items():
  66             #val = swap_order(val, width)
  67             self.st(addr, val, width, swap=False)
  68
  69     def _get_shifter_mask(self, wid, remainder):
  70         shifter = ((self.bytes_per_word - wid) - remainder) * \
  71             8  # bits per byte
  72         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
  73         # BE/LE mode?
  74         shifter = remainder * 8
  75         mask = (1 << (wid * 8)) - 1
  76         print ("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
  77         return shifter, mask
  78
  79     # TODO: Implement ld/st of lesser width
  80     def ld(self, address, width=8, swap=True, check_in_mem=False):
  81         print("ld from addr 0x{:x} width {:d}".format(address, width))
  82         remainder = address & (self.bytes_per_word - 1)
  83         address = address >> self.word_log2
  84         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
  85         if address in self.mem:
  86             val = self.mem[address]
  87         elif check_in_mem:
  88             return None
  89         else:
  90             val = 0
  91         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
  92
  93         if width != self.bytes_per_word:
  94             shifter, mask = self._get_shifter_mask(width, remainder)
  95             print ("masking", hex(val), hex(mask<<shifter), shifter)
  96             val = val & (mask << shifter)
  97             val >>= shifter
  98         if swap:
  99             val = swap_order(val, width)
 100         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
 101         return val
 102
 103     def st(self, addr, v, width=8, swap=True):
 104         staddr = addr
 105         remainder = addr & (self.bytes_per_word - 1)
 106         addr = addr >> self.word_log2
 107         print("Writing 0x{:x} to ST 0x{:x} memaddr 0x{:x}/{:x}".format(v,
 108                         staddr, addr, remainder, swap))
 109         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 110         if swap:
 111             v = swap_order(v, width)
 112         if width != self.bytes_per_word:
 113             if addr in self.mem:
 114                 val = self.mem[addr]
 115             else:
 116                 val = 0
 117             shifter, mask = self._get_shifter_mask(width, remainder)
 118             val &= ~(mask << shifter)
 119             val |= v << shifter
 120             self.mem[addr] = val
 121         else:
 122             self.mem[addr] = v
 123         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 124
 125     def __call__(self, addr, sz):
 126         val = self.ld(addr.value, sz)
 127         print ("memread", addr, sz, val)
 128         return SelectableInt(val, sz*8)
 129
 130     def memassign(self, addr, sz, val):
 131         print ("memassign", addr, sz, val)
 132         self.st(addr.value, val.value, sz)
 133
 134
 135 class GPR(dict):
 136     def __init__(self, decoder, regfile):
 137         dict.__init__(self)
 138         self.sd = decoder
 139         for i in range(32):
 140             self[i] = SelectableInt(regfile[i], 64)
 141
 142     def __call__(self, ridx):
 143         return self[ridx]
 144
 145     def set_form(self, form):
 146         self.form = form
 147
 148     def getz(self, rnum):
 149         #rnum = rnum.value # only SelectableInt allowed
 150         print("GPR getzero", rnum)
 151         if rnum == 0:
 152             return SelectableInt(0, 64)
 153         return self[rnum]
 154
 155     def _get_regnum(self, attr):
 156         getform = self.sd.sigforms[self.form]
 157         rnum = getattr(getform, attr)
 158         return rnum
 159
 160     def ___getitem__(self, attr):
 161         print("GPR getitem", attr)
 162         rnum = self._get_regnum(attr)
 163         return self.regfile[rnum]
 164
 165     def dump(self):
 166         for i in range(0, len(self), 8):
 167             s = []
 168             for j in range(8):
 169                 s.append("%08x" % self[i+j].value)
 170             s = ' '.join(s)
 171             print("reg", "%2d" % i, s)
 172
 173 class PC:
 174     def __init__(self, pc_init=0):
 175         self.CIA = SelectableInt(pc_init, 64)
 176         self.NIA = self.CIA + SelectableInt(4, 64)
 177
 178     def update(self, namespace):
 179         self.CIA = namespace['NIA'].narrow(64)
 180         self.NIA = self.CIA + SelectableInt(4, 64)
 181         namespace['CIA'] = self.CIA
 182         namespace['NIA'] = self.NIA
 183
 184
 185 class SPR(dict):
 186     def __init__(self, dec2, initial_sprs={}):
 187         self.sd = dec2
 188         dict.__init__(self)
 189         self.update(initial_sprs)
 190
 191     def __getitem__(self, key):
 192         # if key in special_sprs get the special spr, otherwise return key
 193         if isinstance(key, SelectableInt):
 194             key = key.value
 195         key = special_sprs.get(key, key)
 196         if key in self:
 197             return dict.__getitem__(self, key)
 198         else:
 199             info = spr_dict[key]
 200             dict.__setitem__(self, key, SelectableInt(0, info.length))
 201             return dict.__getitem__(self, key)
 202
 203     def __setitem__(self, key, value):
 204         if isinstance(key, SelectableInt):
 205             key = key.value
 206         key = special_sprs.get(key, key)
 207         dict.__setitem__(self, key, value)
 208
 209     def __call__(self, ridx):
 210         return self[ridx]
 211
 212
 213 class ISACaller:
 214     # decoder2 - an instance of power_decoder2
 215     # regfile - a list of initial values for the registers
 216     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 217     # respect_pc - tracks the program counter.  requires initial_insns
 218     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 219                        initial_mem=None, initial_msr=0,
 220                        initial_insns=None, respect_pc=False,
 221                        disassembly=None):
 222
 223         self.respect_pc = respect_pc
 224         if initial_sprs is None:
 225             initial_sprs = {}
 226         if initial_mem is None:
 227             initial_mem = {}
 228         if initial_insns is None:
 229             initial_insns = {}
 230             assert self.respect_pc == False, "instructions required to honor pc"
 231
 232         print ("ISACaller insns", respect_pc, initial_insns, disassembly)
 233
 234         # "fake program counter" mode (for unit testing)
 235         self.fake_pc = 0
 236         if not respect_pc:
 237             if isinstance(initial_mem, tuple):
 238                 self.fake_pc = initial_mem[0]
 239
 240         # disassembly: we need this for now (not given from the decoder)
 241         self.disassembly = {}
 242         if disassembly:
 243             for i, code in enumerate(disassembly):
 244                 self.disassembly[i*4 + self.fake_pc] = code
 245
 246         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 247         self.gpr = GPR(decoder2, regfile)
 248         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 249         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 250         self.pc = PC()
 251         self.spr = SPR(decoder2, initial_sprs)
 252         self.msr = SelectableInt(initial_msr, 64) # underlying reg
 253
 254         # TODO, needed here:
 255         # FPR (same as GPR except for FP nums)
 256         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 257         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 258         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 259         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 260         #         -- Done
 261         # 2.3.2 LR   (actually SPR #8) -- Done
 262         # 2.3.3 CTR  (actually SPR #9) -- Done
 263         # 2.3.4 TAR  (actually SPR #815)
 264         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 265         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 266
 267         # create CR then allow portions of it to be "selectable" (below)
 268         self._cr = SelectableInt(initial_cr, 64) # underlying reg
 269         self.cr = FieldSelectableInt(self._cr, list(range(32,64)))
 270
 271         # "undefined", just set to variable-bit-width int (use exts "max")
 272         self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
 273
 274         self.namespace = {'GPR': self.gpr,
 275                           'MEM': self.mem,
 276                           'SPR': self.spr,
 277                           'memassign': self.memassign,
 278                           'NIA': self.pc.NIA,
 279                           'CIA': self.pc.CIA,
 280                           'CR': self.cr,
 281                           'MSR': self.msr,
 282                           'undefined': self.undefined,
 283                           'mode_is_64bit': True,
 284                           'SO': XER_bits['SO']
 285                           }
 286
 287         # field-selectable versions of Condition Register TODO check bitranges?
 288         self.crl = []
 289         for i in range(8):
 290             bits = tuple(range(i*4, (i+1)*4))# errr... maybe?
 291             _cr = FieldSelectableInt(self.cr, bits)
 292             self.crl.append(_cr)
 293             self.namespace["CR%d" % i] = _cr
 294
 295         self.decoder = decoder2.dec
 296         self.dec2 = decoder2
 297
 298     def TRAP(self, trap_addr=0x700):
 299         print ("TRAP: TODO")
 300         # store CIA(+4?) in SRR0, set NIA to 0x700
 301         # store MSR in SRR1, set MSR to um errr something, have to check spec
 302
 303     def memassign(self, ea, sz, val):
 304         self.mem.memassign(ea, sz, val)
 305
 306     def prep_namespace(self, formname, op_fields):
 307         # TODO: get field names from form in decoder*1* (not decoder2)
 308         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 309         # from spec
 310         # then "yield" fields only from op_fields rather than hard-coded
 311         # list, here.
 312         fields = self.decoder.sigforms[formname]
 313         for name in op_fields:
 314             if name == 'spr':
 315                 sig = getattr(fields, name.upper())
 316             else:
 317                 sig = getattr(fields, name)
 318             val = yield sig
 319             if name in ['BF', 'BFA']:
 320                 self.namespace[name] = val
 321             else:
 322                 self.namespace[name] = SelectableInt(val, sig.width)
 323
 324         self.namespace['XER'] = self.spr['XER']
 325         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 326         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 327
 328     def handle_carry_(self, inputs, outputs, already_done):
 329         inv_a = yield self.dec2.e.invert_a
 330         if inv_a:
 331             inputs[0] = ~inputs[0]
 332
 333         imm_ok = yield self.dec2.e.imm_data.ok
 334         if imm_ok:
 335             imm = yield self.dec2.e.imm_data.data
 336             inputs.append(SelectableInt(imm, 64))
 337         assert len(outputs) >= 1
 338         print ("outputs", repr(outputs))
 339         if isinstance(outputs, list) or isinstance(outputs, tuple):
 340             output = outputs[0]
 341         else:
 342             output = outputs
 343         gts = []
 344         for x in inputs:
 345             print ("gt input", x, output)
 346             gt = (x > output)
 347             gts.append(gt)
 348         print(gts)
 349         cy = 1 if any(gts) else 0
 350         if not (1 & already_done):
 351             self.spr['XER'][XER_bits['CA']] = cy
 352
 353         print ("inputs", inputs)
 354         # 32 bit carry
 355         gts = []
 356         for x in inputs:
 357             print ("input", x, output)
 358             gt = (x[32:64] > output[32:64]) == SelectableInt(1, 1)
 359             gts.append(gt)
 360         cy32 = 1 if any(gts) else 0
 361         if not (2 & already_done):
 362             self.spr['XER'][XER_bits['CA32']] = cy32
 363
 364     def handle_overflow(self, inputs, outputs):
 365         inv_a = yield self.dec2.e.invert_a
 366         if inv_a:
 367             inputs[0] = ~inputs[0]
 368
 369         imm_ok = yield self.dec2.e.imm_data.ok
 370         if imm_ok:
 371             imm = yield self.dec2.e.imm_data.data
 372             inputs.append(SelectableInt(imm, 64))
 373         assert len(outputs) >= 1
 374         print ("handle_overflow", inputs, outputs)
 375         if len(inputs) >= 2:
 376             output = outputs[0]
 377
 378             # OV (64-bit)
 379             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 380             output_sgn = exts(output.value, output.bits) < 0
 381             ov = 1 if input_sgn[0] == input_sgn[1] and \
 382                 output_sgn != input_sgn[0] else 0
 383
 384             # OV (32-bit)
 385             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 386             output32_sgn = exts(output.value, 32) < 0
 387             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 388                 output32_sgn != input32_sgn[0] else 0
 389
 390             self.spr['XER'][XER_bits['OV']] = ov
 391             self.spr['XER'][XER_bits['OV32']] = ov32
 392             so = self.spr['XER'][XER_bits['SO']]
 393             so = so | ov
 394             self.spr['XER'][XER_bits['SO']] = so
 395
 396     def handle_comparison(self, outputs):
 397         out = outputs[0]
 398         out = exts(out.value, out.bits)
 399         zero = SelectableInt(out == 0, 1)
 400         positive = SelectableInt(out > 0, 1)
 401         negative = SelectableInt(out < 0, 1)
 402         SO = self.spr['XER'][XER_bits['SO']]
 403         cr_field = selectconcat(negative, positive, zero, SO)
 404         self.crl[0].eq(cr_field)
 405
 406     def set_pc(self, pc_val):
 407         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 408         self.pc.update(self.namespace)
 409
 410     def setup_one(self):
 411         """set up one instruction
 412         """
 413         if self.respect_pc:
 414             pc = self.pc.CIA.value
 415         else:
 416             pc = self.fake_pc
 417         self._pc = pc
 418         ins = self.imem.ld(pc, 4, False, True)
 419         if ins is None:
 420             raise KeyError("no instruction at 0x%x" % pc)
 421         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 422         print ("NIA, CIA", self.pc.CIA.value, self.pc.NIA.value)
 423
 424         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 425         yield self.dec2.dec.bigendian.eq(0)  # little / big?
 426
 427     def execute_one(self):
 428         """execute one instruction
 429         """
 430         # get the disassembly code for this instruction
 431         code = self.disassembly[self._pc]
 432         print("sim-execute", hex(self._pc), code)
 433         opname = code.split(' ')[0]
 434         yield from self.call(opname)
 435
 436         if not self.respect_pc:
 437             self.fake_pc += 4
 438         print ("NIA, CIA", self.pc.CIA.value, self.pc.NIA.value)
 439
 440     def get_assembly_name(self):
 441         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 442         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 443         asmcode = yield self.dec2.dec.op.asmcode
 444         asmop = insns.get(asmcode, None)
 445
 446         # sigh reconstruct the assembly instruction name
 447         ov_en = yield self.dec2.e.oe.oe
 448         ov_ok = yield self.dec2.e.oe.ok
 449         if ov_en & ov_ok:
 450             asmop += "."
 451         lk = yield self.dec2.e.lk
 452         if lk:
 453             asmop += "l"
 454         int_op = yield self.dec2.dec.op.internal_op
 455         print ("int_op", int_op)
 456         if int_op in [InternalOp.OP_B.value, InternalOp.OP_BC.value]:
 457             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 458             print ("AA", AA)
 459             if AA:
 460                 asmop += "a"
 461         if int_op == InternalOp.OP_MFCR.value:
 462             dec_insn = yield self.dec2.e.insn
 463             if dec_insn & (1<<20) != 0: # sigh
 464                 asmop = 'mfocrf'
 465             else:
 466                 asmop = 'mfcr'
 467         # XXX TODO: for whatever weird reason this doesn't work
 468         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 469         if int_op == InternalOp.OP_MTCRF.value:
 470             dec_insn = yield self.dec2.e.insn
 471             if dec_insn & (1<<20) != 0: # sigh
 472                 asmop = 'mtocrf'
 473             else:
 474                 asmop = 'mtcrf'
 475         return asmop
 476
 477     def call(self, name):
 478         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 479         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 480         asmop = yield from self.get_assembly_name()
 481         print  ("call", name, asmop)
 482         if name not in ['mtcrf', 'mtocrf']:
 483             assert name == asmop, "name %s != %s" % (name, asmop)
 484
 485         info = self.instrs[name]
 486         yield from self.prep_namespace(info.form, info.op_fields)
 487
 488         # preserve order of register names
 489         input_names = create_args(list(info.read_regs) + list(info.uninit_regs))
 490         print(input_names)
 491
 492         # main registers (RT, RA ...)
 493         inputs = []
 494         for name in input_names:
 495             regnum = yield getattr(self.decoder, name)
 496             regname = "_" + name
 497             self.namespace[regname] = regnum
 498             print('reading reg %d' % regnum)
 499             inputs.append(self.gpr(regnum))
 500
 501         # "special" registers
 502         for special in info.special_regs:
 503             if special in special_sprs:
 504                 inputs.append(self.spr[special])
 505             else:
 506                 inputs.append(self.namespace[special])
 507
 508         print(inputs)
 509         results = info.func(self, *inputs)
 510         print(results)
 511
 512         # detect if CA/CA32 already in outputs (sra*, basically)
 513         already_done = 0
 514         if info.write_regs:
 515             output_names = create_args(info.write_regs)
 516             for name in output_names:
 517                 if name == 'CA':
 518                     already_done |= 1
 519                 if name == 'CA32':
 520                     already_done |= 2
 521
 522         print ("carry already done?", bin(already_done))
 523         carry_en = yield self.dec2.e.output_carry
 524         if carry_en:
 525             yield from self.handle_carry_(inputs, results, already_done)
 526         ov_en = yield self.dec2.e.oe.oe
 527         ov_ok = yield self.dec2.e.oe.ok
 528         if ov_en & ov_ok:
 529             yield from self.handle_overflow(inputs, results)
 530         rc_en = yield self.dec2.e.rc.data
 531         if rc_en:
 532             self.handle_comparison(results)
 533
 534         # any modified return results?
 535         if info.write_regs:
 536             for name, output in zip(output_names, results):
 537                 if isinstance(output, int):
 538                     output = SelectableInt(output, 256)
 539                 if name in ['CA', 'CA32']:
 540                     if carry_en:
 541                         print ("writing %s to XER" % name, output)
 542                         self.spr['XER'][XER_bits[name]] = output.value
 543                     else:
 544                         print ("NOT writing %s to XER" % name, output)
 545                 elif name in info.special_regs:
 546                     print('writing special %s' % name, output, special_sprs)
 547                     if name in special_sprs:
 548                         self.spr[name] = output
 549                     else:
 550                         self.namespace[name].eq(output)
 551                 else:
 552                     regnum = yield getattr(self.decoder, name)
 553                     print('writing reg %d %s' % (regnum, str(output)))
 554                     if output.bits > 64:
 555                         output = SelectableInt(output.value, 64)
 556                     self.gpr[regnum] = output
 557
 558         # update program counter
 559         self.pc.update(self.namespace)
 560
 561
 562 def inject():
 563     """Decorator factory.
 564
 565     this decorator will "inject" variables into the function's namespace,
 566     from the *dictionary* in self.namespace.  it therefore becomes possible
 567     to make it look like a whole stack of variables which would otherwise
 568     need "self." inserted in front of them (*and* for those variables to be
 569     added to the instance) "appear" in the function.
 570
 571     "self.namespace['SI']" for example becomes accessible as just "SI" but
 572     *only* inside the function, when decorated.
 573     """
 574     def variable_injector(func):
 575         @wraps(func)
 576         def decorator(*args, **kwargs):
 577             try:
 578                 func_globals = func.__globals__  # Python 2.6+
 579             except AttributeError:
 580                 func_globals = func.func_globals  # Earlier versions.
 581
 582             context = args[0].namespace # variables to be injected
 583             saved_values = func_globals.copy()  # Shallow copy of dict.
 584             func_globals.update(context)
 585             result = func(*args, **kwargs)
 586             args[0].namespace = func_globals
 587             #exec (func.__code__, func_globals)
 588
 589             #finally:
 590             #    func_globals = saved_values  # Undo changes.
 591
 592             return result
 593
 594         return decorator
 595
 596     return variable_injector
 597