aeecc897a3ae4168187691e0f2cfc619dfc81ed2
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
16 from nmigen
.back
.pysim
import Settle
17 from functools
import wraps
19 from soc
.decoder
.orderedset
import OrderedSet
20 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
22 from soc
.decoder
.power_enums
import (spr_dict
, spr_byname
, XER_bits
,
23 insns
, MicrOp
, In1Sel
, In2Sel
, In3Sel
,
25 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
26 from soc
.consts
import PIb
, MSRb
# big-endian (PowerISA versions)
27 from soc
.decoder
.power_svp64
import SVP64RM
, decode_extra
29 from collections
import namedtuple
33 instruction_info
= namedtuple('instruction_info',
34 'func read_regs uninit_regs write_regs ' +
35 'special_regs op_fields form asmregs')
45 def swap_order(x
, nbytes
):
46 x
= x
.to_bytes(nbytes
, byteorder
='little')
47 x
= int.from_bytes(x
, byteorder
='big', signed
=False)
52 # TODO (lkcl): adjust other registers that should be in a particular order
53 # probably CA, CA32, and CR
70 def create_args(reglist
, extra
=None):
71 retval
= list(OrderedSet(reglist
))
72 retval
.sort(key
=lambda reg
: REG_SORT_ORDER
[reg
])
74 return [extra
] + retval
80 def __init__(self
, row_bytes
=8, initial_mem
=None):
82 self
.bytes_per_word
= row_bytes
83 self
.word_log2
= math
.ceil(math
.log2(row_bytes
))
84 print("Sim-Mem", initial_mem
, self
.bytes_per_word
, self
.word_log2
)
88 # different types of memory data structures recognised (for convenience)
89 if isinstance(initial_mem
, list):
90 initial_mem
= (0, initial_mem
)
91 if isinstance(initial_mem
, tuple):
92 startaddr
, mem
= initial_mem
94 for i
, val
in enumerate(mem
):
95 initial_mem
[startaddr
+ row_bytes
*i
] = (val
, row_bytes
)
97 for addr
, (val
, width
) in initial_mem
.items():
98 #val = swap_order(val, width)
99 self
.st(addr
, val
, width
, swap
=False)
101 def _get_shifter_mask(self
, wid
, remainder
):
102 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
104 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
106 shifter
= remainder
* 8
107 mask
= (1 << (wid
* 8)) - 1
108 print("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
111 # TODO: Implement ld/st of lesser width
112 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
113 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
114 remainder
= address
& (self
.bytes_per_word
- 1)
115 address
= address
>> self
.word_log2
116 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
117 if address
in self
.mem
:
118 val
= self
.mem
[address
]
123 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
125 if width
!= self
.bytes_per_word
:
126 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
127 print("masking", hex(val
), hex(mask
<< shifter
), shifter
)
128 val
= val
& (mask
<< shifter
)
131 val
= swap_order(val
, width
)
132 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
135 def st(self
, addr
, v
, width
=8, swap
=True):
137 remainder
= addr
& (self
.bytes_per_word
- 1)
138 addr
= addr
>> self
.word_log2
139 print("Writing 0x{:x} to ST 0x{:x} "
140 "memaddr 0x{:x}/{:x}".format(v
, staddr
, addr
, remainder
, swap
))
141 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
143 v
= swap_order(v
, width
)
144 if width
!= self
.bytes_per_word
:
149 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
150 val
&= ~
(mask
<< shifter
)
155 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
157 def __call__(self
, addr
, sz
):
158 val
= self
.ld(addr
.value
, sz
, swap
=False)
159 print("memread", addr
, sz
, val
)
160 return SelectableInt(val
, sz
*8)
162 def memassign(self
, addr
, sz
, val
):
163 print("memassign", addr
, sz
, val
)
164 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
168 def __init__(self
, decoder
, isacaller
, svstate
, regfile
):
171 self
.isacaller
= isacaller
172 self
.svstate
= svstate
174 self
[i
] = SelectableInt(regfile
[i
], 64)
176 def __call__(self
, ridx
):
179 def set_form(self
, form
):
182 def getz(self
, rnum
):
183 # rnum = rnum.value # only SelectableInt allowed
184 print("GPR getzero", rnum
)
186 return SelectableInt(0, 64)
189 def _get_regnum(self
, attr
):
190 getform
= self
.sd
.sigforms
[self
.form
]
191 rnum
= getattr(getform
, attr
)
194 def ___getitem__(self
, attr
):
195 """ XXX currently not used
197 rnum
= self
._get
_regnum
(attr
)
198 offs
= self
.svstate
.srcstep
199 print("GPR getitem", attr
, rnum
, "srcoffs", offs
)
200 return self
.regfile
[rnum
]
203 for i
in range(0, len(self
), 8):
206 s
.append("%08x" % self
[i
+j
].value
)
208 print("reg", "%2d" % i
, s
)
212 def __init__(self
, pc_init
=0):
213 self
.CIA
= SelectableInt(pc_init
, 64)
214 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
216 def update(self
, namespace
):
217 self
.CIA
= namespace
['NIA'].narrow(64)
218 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
219 namespace
['CIA'] = self
.CIA
220 namespace
['NIA'] = self
.NIA
223 # Simple-V: see https://libre-soc.org/openpower/sv
225 def __init__(self
, init
=0):
226 self
.spr
= SelectableInt(init
, 32)
227 # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
228 self
.maxvl
= FieldSelectableInt(self
.spr
, tuple(range(0,7)))
229 self
.vl
= FieldSelectableInt(self
.spr
, tuple(range(7,14)))
230 self
.srcstep
= FieldSelectableInt(self
.spr
, tuple(range(14,21)))
231 self
.dststep
= FieldSelectableInt(self
.spr
, tuple(range(21,28)))
232 self
.subvl
= FieldSelectableInt(self
.spr
, tuple(range(28,30)))
233 self
.svstep
= FieldSelectableInt(self
.spr
, tuple(range(30,32)))
238 def __init__(self
, init
=0):
239 self
.spr
= SelectableInt(init
, 24)
240 # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
241 self
.mmode
= FieldSelectableInt(self
.spr
, [0])
242 self
.mask
= FieldSelectableInt(self
.spr
, tuple(range(1,4)))
243 self
.elwidth
= FieldSelectableInt(self
.spr
, tuple(range(4,6)))
244 self
.ewsrc
= FieldSelectableInt(self
.spr
, tuple(range(6,8)))
245 self
.subvl
= FieldSelectableInt(self
.spr
, tuple(range(8,10)))
246 self
.extra
= FieldSelectableInt(self
.spr
, tuple(range(10,19)))
247 self
.mode
= FieldSelectableInt(self
.spr
, tuple(range(19,24)))
250 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
251 class SVP64PrefixFields
:
253 self
.insn
= SelectableInt(0, 32)
254 # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
255 self
.major
= FieldSelectableInt(self
.insn
, tuple(range(0,6)))
256 self
.pid
= FieldSelectableInt(self
.insn
, (7, 9)) # must be 0b11
257 rmfields
= [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
258 self
.rm
= FieldSelectableInt(self
.insn
, rmfields
)
262 def __init__(self
, dec2
, initial_sprs
={}):
265 for key
, v
in initial_sprs
.items():
266 if isinstance(key
, SelectableInt
):
268 key
= special_sprs
.get(key
, key
)
269 if isinstance(key
, int):
272 info
= spr_byname
[key
]
273 if not isinstance(v
, SelectableInt
):
274 v
= SelectableInt(v
, info
.length
)
277 def __getitem__(self
, key
):
278 print("get spr", key
)
279 print("dict", self
.items())
280 # if key in special_sprs get the special spr, otherwise return key
281 if isinstance(key
, SelectableInt
):
283 if isinstance(key
, int):
284 key
= spr_dict
[key
].SPR
285 key
= special_sprs
.get(key
, key
)
286 if key
== 'HSRR0': # HACK!
288 if key
== 'HSRR1': # HACK!
291 res
= dict.__getitem
__(self
, key
)
293 if isinstance(key
, int):
296 info
= spr_byname
[key
]
297 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
298 res
= dict.__getitem
__(self
, key
)
299 print("spr returning", key
, res
)
302 def __setitem__(self
, key
, value
):
303 if isinstance(key
, SelectableInt
):
305 if isinstance(key
, int):
306 key
= spr_dict
[key
].SPR
307 print("spr key", key
)
308 key
= special_sprs
.get(key
, key
)
309 if key
== 'HSRR0': # HACK!
310 self
.__setitem
__('SRR0', value
)
311 if key
== 'HSRR1': # HACK!
312 self
.__setitem
__('SRR1', value
)
313 print("setting spr", key
, value
)
314 dict.__setitem
__(self
, key
, value
)
316 def __call__(self
, ridx
):
319 def get_pdecode_idx_in(dec2
, name
):
321 in1_sel
= yield op
.in1_sel
322 in2_sel
= yield op
.in2_sel
323 in3_sel
= yield op
.in3_sel
324 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
325 in1
= yield dec2
.e
.read_reg1
.data
326 in2
= yield dec2
.e
.read_reg2
.data
327 in3
= yield dec2
.e
.read_reg3
.data
328 in1_isvec
= yield dec2
.in1_isvec
329 in2_isvec
= yield dec2
.in2_isvec
330 in3_isvec
= yield dec2
.in3_isvec
331 print ("get_pdecode_idx", in1_sel
, In1Sel
.RA
.value
, in1
, in1_isvec
)
332 # identify which regnames map to in1/2/3
334 if (in1_sel
== In1Sel
.RA
.value
or
335 (in1_sel
== In1Sel
.RA_OR_ZERO
.value
and in1
!= 0)):
336 return in1
, in1_isvec
337 if in1_sel
== In1Sel
.RA_OR_ZERO
.value
:
338 return in1
, in1_isvec
340 if in2_sel
== In2Sel
.RB
.value
:
341 return in2
, in2_isvec
342 if in3_sel
== In3Sel
.RB
.value
:
343 return in3
, in3_isvec
344 # XXX TODO, RC doesn't exist yet!
346 assert False, "RC does not exist yet"
348 if in1_sel
== In1Sel
.RS
.value
:
349 return in1
, in1_isvec
350 if in2_sel
== In2Sel
.RS
.value
:
351 return in2
, in2_isvec
352 if in3_sel
== In3Sel
.RS
.value
:
353 return in3
, in3_isvec
357 def get_pdecode_idx_out(dec2
, name
):
359 out_sel
= yield op
.out_sel
360 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
361 out
= yield dec2
.e
.write_reg
.data
362 o_isvec
= yield dec2
.o_isvec
363 print ("get_pdecode_idx_out", out_sel
, OutSel
.RA
.value
, out
, o_isvec
)
364 # identify which regnames map to out / o2
366 if out_sel
== OutSel
.RA
.value
:
369 if out_sel
== OutSel
.RT
.value
:
375 def get_pdecode_idx_out2(dec2
, name
):
377 print ("TODO: get_pdecode_idx_out2", name
)
382 # decoder2 - an instance of power_decoder2
383 # regfile - a list of initial values for the registers
384 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
385 # respect_pc - tracks the program counter. requires initial_insns
386 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
387 initial_mem
=None, initial_msr
=0,
389 initial_insns
=None, respect_pc
=False,
394 self
.bigendian
= bigendian
396 self
.is_svp64_mode
= False
397 self
.respect_pc
= respect_pc
398 if initial_sprs
is None:
400 if initial_mem
is None:
402 if initial_insns
is None:
404 assert self
.respect_pc
== False, "instructions required to honor pc"
406 print("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
407 print("ISACaller initial_msr", initial_msr
)
409 # "fake program counter" mode (for unit testing)
413 if isinstance(initial_mem
, tuple):
414 self
.fake_pc
= initial_mem
[0]
415 disasm_start
= self
.fake_pc
417 disasm_start
= initial_pc
419 # disassembly: we need this for now (not given from the decoder)
420 self
.disassembly
= {}
422 for i
, code
in enumerate(disassembly
):
423 self
.disassembly
[i
*4 + disasm_start
] = code
425 # set up registers, instruction memory, data memory, PC, SPRs, MSR
426 self
.svp64rm
= SVP64RM()
427 self
.svstate
= SVP64State(initial_svstate
)
428 self
.gpr
= GPR(decoder2
, self
, self
.svstate
, regfile
)
429 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
430 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
432 self
.spr
= SPR(decoder2
, initial_sprs
)
433 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
436 # FPR (same as GPR except for FP nums)
437 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
438 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
439 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
440 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
442 # 2.3.2 LR (actually SPR #8) -- Done
443 # 2.3.3 CTR (actually SPR #9) -- Done
444 # 2.3.4 TAR (actually SPR #815)
445 # 3.2.2 p45 XER (actually SPR #1) -- Done
446 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
448 # create CR then allow portions of it to be "selectable" (below)
449 #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
450 self
.cr
= SelectableInt(initial_cr
, 64) # underlying reg
451 #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
453 # "undefined", just set to variable-bit-width int (use exts "max")
454 #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
457 self
.namespace
.update(self
.spr
)
458 self
.namespace
.update({'GPR': self
.gpr
,
461 'memassign': self
.memassign
,
466 'undefined': undefined
,
467 'mode_is_64bit': True,
471 # update pc to requested start point
472 self
.set_pc(initial_pc
)
474 # field-selectable versions of Condition Register TODO check bitranges?
477 bits
= tuple(range(i
*4+32, (i
+1)*4+32)) # errr... maybe?
478 _cr
= FieldSelectableInt(self
.cr
, bits
)
480 self
.namespace
["CR%d" % i
] = _cr
482 self
.decoder
= decoder2
.dec
485 def TRAP(self
, trap_addr
=0x700, trap_bit
=PIb
.TRAP
):
486 print("TRAP:", hex(trap_addr
), hex(self
.namespace
['MSR'].value
))
487 # store CIA(+4?) in SRR0, set NIA to 0x700
488 # store MSR in SRR1, set MSR to um errr something, have to check spec
489 self
.spr
['SRR0'].value
= self
.pc
.CIA
.value
490 self
.spr
['SRR1'].value
= self
.namespace
['MSR'].value
491 self
.trap_nia
= SelectableInt(trap_addr
, 64)
492 self
.spr
['SRR1'][trap_bit
] = 1 # change *copy* of MSR in SRR1
494 # set exception bits. TODO: this should, based on the address
495 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
496 # bits appropriately. however it turns out that *for now* in all
497 # cases (all trap_addrs) the exact same thing is needed.
498 self
.msr
[MSRb
.IR
] = 0
499 self
.msr
[MSRb
.DR
] = 0
500 self
.msr
[MSRb
.FE0
] = 0
501 self
.msr
[MSRb
.FE1
] = 0
502 self
.msr
[MSRb
.EE
] = 0
503 self
.msr
[MSRb
.RI
] = 0
504 self
.msr
[MSRb
.SF
] = 1
505 self
.msr
[MSRb
.TM
] = 0
506 self
.msr
[MSRb
.VEC
] = 0
507 self
.msr
[MSRb
.VSX
] = 0
508 self
.msr
[MSRb
.PR
] = 0
509 self
.msr
[MSRb
.FP
] = 0
510 self
.msr
[MSRb
.PMM
] = 0
511 self
.msr
[MSRb
.TEs
] = 0
512 self
.msr
[MSRb
.TEe
] = 0
513 self
.msr
[MSRb
.UND
] = 0
514 self
.msr
[MSRb
.LE
] = 1
516 def memassign(self
, ea
, sz
, val
):
517 self
.mem
.memassign(ea
, sz
, val
)
519 def prep_namespace(self
, formname
, op_fields
):
520 # TODO: get field names from form in decoder*1* (not decoder2)
521 # decoder2 is hand-created, and decoder1.sigform is auto-generated
523 # then "yield" fields only from op_fields rather than hard-coded
525 fields
= self
.decoder
.sigforms
[formname
]
526 for name
in op_fields
:
528 sig
= getattr(fields
, name
.upper())
530 sig
= getattr(fields
, name
)
532 # these are all opcode fields involved in index-selection of CR,
533 # and need to do "standard" arithmetic. CR[BA+32] for example
534 # would, if using SelectableInt, only be 5-bit.
535 if name
in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
536 self
.namespace
[name
] = val
538 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
540 self
.namespace
['XER'] = self
.spr
['XER']
541 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
542 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
544 def handle_carry_(self
, inputs
, outputs
, already_done
):
545 inv_a
= yield self
.dec2
.e
.do
.invert_in
547 inputs
[0] = ~inputs
[0]
549 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
551 imm
= yield self
.dec2
.e
.do
.imm_data
.data
552 inputs
.append(SelectableInt(imm
, 64))
553 assert len(outputs
) >= 1
554 print("outputs", repr(outputs
))
555 if isinstance(outputs
, list) or isinstance(outputs
, tuple):
561 print("gt input", x
, output
)
562 gt
= (gtu(x
, output
))
565 cy
= 1 if any(gts
) else 0
567 if not (1 & already_done
):
568 self
.spr
['XER'][XER_bits
['CA']] = cy
570 print("inputs", already_done
, inputs
)
572 # ARGH... different for OP_ADD... *sigh*...
573 op
= yield self
.dec2
.e
.do
.insn_type
574 if op
== MicrOp
.OP_ADD
.value
:
575 res32
= (output
.value
& (1 << 32)) != 0
576 a32
= (inputs
[0].value
& (1 << 32)) != 0
578 b32
= (inputs
[1].value
& (1 << 32)) != 0
581 cy32
= res32 ^ a32 ^ b32
582 print("CA32 ADD", cy32
)
586 print("input", x
, output
)
587 print(" x[32:64]", x
, x
[32:64])
588 print(" o[32:64]", output
, output
[32:64])
589 gt
= (gtu(x
[32:64], output
[32:64])) == SelectableInt(1, 1)
591 cy32
= 1 if any(gts
) else 0
592 print("CA32", cy32
, gts
)
593 if not (2 & already_done
):
594 self
.spr
['XER'][XER_bits
['CA32']] = cy32
596 def handle_overflow(self
, inputs
, outputs
, div_overflow
):
597 if hasattr(self
.dec2
.e
.do
, "invert_in"):
598 inv_a
= yield self
.dec2
.e
.do
.invert_in
600 inputs
[0] = ~inputs
[0]
602 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
604 imm
= yield self
.dec2
.e
.do
.imm_data
.data
605 inputs
.append(SelectableInt(imm
, 64))
606 assert len(outputs
) >= 1
607 print("handle_overflow", inputs
, outputs
, div_overflow
)
608 if len(inputs
) < 2 and div_overflow
is None:
611 # div overflow is different: it's returned by the pseudo-code
612 # because it's more complex than can be done by analysing the output
613 if div_overflow
is not None:
614 ov
, ov32
= div_overflow
, div_overflow
615 # arithmetic overflow can be done by analysing the input and output
616 elif len(inputs
) >= 2:
620 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
621 output_sgn
= exts(output
.value
, output
.bits
) < 0
622 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
623 output_sgn
!= input_sgn
[0] else 0
626 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
627 output32_sgn
= exts(output
.value
, 32) < 0
628 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
629 output32_sgn
!= input32_sgn
[0] else 0
631 self
.spr
['XER'][XER_bits
['OV']] = ov
632 self
.spr
['XER'][XER_bits
['OV32']] = ov32
633 so
= self
.spr
['XER'][XER_bits
['SO']]
635 self
.spr
['XER'][XER_bits
['SO']] = so
637 def handle_comparison(self
, outputs
):
639 assert isinstance(out
, SelectableInt
), \
640 "out zero not a SelectableInt %s" % repr(outputs
)
641 print("handle_comparison", out
.bits
, hex(out
.value
))
642 # TODO - XXX *processor* in 32-bit mode
643 # https://bugs.libre-soc.org/show_bug.cgi?id=424
645 # o32 = exts(out.value, 32)
646 # print ("handle_comparison exts 32 bit", hex(o32))
647 out
= exts(out
.value
, out
.bits
)
648 print("handle_comparison exts", hex(out
))
649 zero
= SelectableInt(out
== 0, 1)
650 positive
= SelectableInt(out
> 0, 1)
651 negative
= SelectableInt(out
< 0, 1)
652 SO
= self
.spr
['XER'][XER_bits
['SO']]
653 print("handle_comparison SO", SO
)
654 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
655 self
.crl
[0].eq(cr_field
)
657 def set_pc(self
, pc_val
):
658 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
659 self
.pc
.update(self
.namespace
)
662 """set up one instruction
665 pc
= self
.pc
.CIA
.value
669 ins
= self
.imem
.ld(pc
, 4, False, True)
671 raise KeyError("no instruction at 0x%x" % pc
)
672 print("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
673 print("CIA NIA", self
.respect_pc
, self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
675 yield self
.dec2
.sv_rm
.eq(0)
676 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
677 yield self
.dec2
.dec
.bigendian
.eq(self
.bigendian
)
678 yield self
.dec2
.state
.msr
.eq(self
.msr
.value
)
679 yield self
.dec2
.state
.pc
.eq(pc
)
681 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
683 opcode
= yield self
.dec2
.dec
.opcode_in
684 pfx
= SVP64PrefixFields()
685 pfx
.insn
.value
= opcode
686 major
= pfx
.major
.asint(msb0
=True) # MSB0 inversion
687 print ("prefix test: opcode:", major
, bin(major
),
688 pfx
.insn
[7] == 0b1, pfx
.insn
[9] == 0b1)
689 self
.is_svp64_mode
= ((major
== 0b000001) and
690 pfx
.insn
[7].value
== 0b1 and
691 pfx
.insn
[9].value
== 0b1)
692 if not self
.is_svp64_mode
:
695 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
696 print ("svp64.rm", bin(pfx
.rm
.asint(msb0
=True)))
697 sv_rm
= pfx
.rm
.asint()
698 ins
= self
.imem
.ld(pc
+4, 4, False, True)
699 print(" svsetup: 0x%x 0x%x %s" % (pc
+4, ins
& 0xffffffff, bin(ins
)))
700 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff) # v3.0B suffix
701 yield self
.dec2
.sv_rm
.eq(sv_rm
) # svp64 prefix
704 def execute_one(self
):
705 """execute one instruction
707 # get the disassembly code for this instruction
708 if self
.is_svp64_mode
:
709 code
= self
.disassembly
[self
._pc
+4]
710 print(" svp64 sim-execute", hex(self
._pc
), code
)
712 code
= self
.disassembly
[self
._pc
]
713 print("sim-execute", hex(self
._pc
), code
)
714 opname
= code
.split(' ')[0]
715 yield from self
.call(opname
)
717 if not self
.respect_pc
:
719 print("execute one, CIA NIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
721 def get_assembly_name(self
):
722 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
723 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
724 dec_insn
= yield self
.dec2
.e
.do
.insn
725 asmcode
= yield self
.dec2
.dec
.op
.asmcode
726 print("get assembly name asmcode", asmcode
, hex(dec_insn
))
727 asmop
= insns
.get(asmcode
, None)
728 int_op
= yield self
.dec2
.dec
.op
.internal_op
730 # sigh reconstruct the assembly instruction name
731 if hasattr(self
.dec2
.e
.do
, "oe"):
732 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
733 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
737 if hasattr(self
.dec2
.e
.do
, "rc"):
738 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
739 rc_ok
= yield self
.dec2
.e
.do
.rc
.ok
743 # grrrr have to special-case MUL op (see DecodeOE)
744 print("ov %d en %d rc %d en %d op %d" %
745 (ov_ok
, ov_en
, rc_ok
, rc_en
, int_op
))
746 if int_op
in [MicrOp
.OP_MUL_H64
.value
, MicrOp
.OP_MUL_H32
.value
]:
751 if not asmop
.endswith("."): # don't add "." to "andis."
754 if hasattr(self
.dec2
.e
.do
, "lk"):
755 lk
= yield self
.dec2
.e
.do
.lk
758 print("int_op", int_op
)
759 if int_op
in [MicrOp
.OP_B
.value
, MicrOp
.OP_BC
.value
]:
760 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
764 spr_msb
= yield from self
.get_spr_msb()
765 if int_op
== MicrOp
.OP_MFCR
.value
:
770 # XXX TODO: for whatever weird reason this doesn't work
771 # https://bugs.libre-soc.org/show_bug.cgi?id=390
772 if int_op
== MicrOp
.OP_MTCRF
.value
:
779 def get_spr_msb(self
):
780 dec_insn
= yield self
.dec2
.e
.do
.insn
781 return dec_insn
& (1 << 20) != 0 # sigh - XFF.spr[-1]?
783 def call(self
, name
):
784 """call(opcode) - the primary execution point for instructions
786 name
= name
.strip() # remove spaces if not already done so
788 print("halted - not executing", name
)
791 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
792 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
793 asmop
= yield from self
.get_assembly_name()
794 print("call", name
, asmop
)
797 int_op
= yield self
.dec2
.dec
.op
.internal_op
798 spr_msb
= yield from self
.get_spr_msb()
800 instr_is_privileged
= False
801 if int_op
in [MicrOp
.OP_ATTN
.value
,
802 MicrOp
.OP_MFMSR
.value
,
803 MicrOp
.OP_MTMSR
.value
,
804 MicrOp
.OP_MTMSRD
.value
,
806 MicrOp
.OP_RFID
.value
]:
807 instr_is_privileged
= True
808 if int_op
in [MicrOp
.OP_MFSPR
.value
,
809 MicrOp
.OP_MTSPR
.value
] and spr_msb
:
810 instr_is_privileged
= True
812 print("is priv", instr_is_privileged
, hex(self
.msr
.value
),
814 # check MSR priv bit and whether op is privileged: if so, throw trap
815 if instr_is_privileged
and self
.msr
[MSRb
.PR
] == 1:
816 self
.TRAP(0x700, PIb
.PRIV
)
817 self
.namespace
['NIA'] = self
.trap_nia
818 self
.pc
.update(self
.namespace
)
821 # check halted condition
826 # check illegal instruction
828 if name
not in ['mtcrf', 'mtocrf']:
829 illegal
= name
!= asmop
832 print("illegal", name
, asmop
)
833 self
.TRAP(0x700, PIb
.ILLEG
)
834 self
.namespace
['NIA'] = self
.trap_nia
835 self
.pc
.update(self
.namespace
)
836 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
837 (name
, asmop
, self
.pc
.CIA
.value
))
840 info
= self
.instrs
[name
]
841 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
843 # preserve order of register names
844 input_names
= create_args(list(info
.read_regs
) +
845 list(info
.uninit_regs
))
848 # get SVP64 entry for the current instruction
849 sv_rm
= self
.svp64rm
.instrs
.get(name
)
850 if sv_rm
is not None:
851 dest_cr
, src_cr
, src_byname
, dest_byname
= decode_extra(sv_rm
)
853 dest_cr
, src_cr
, src_byname
, dest_byname
= False, False, {}, {}
854 print ("sv rm", sv_rm
, dest_cr
, src_cr
, src_byname
, dest_byname
)
856 # main input registers (RT, RA ...)
858 for name
in input_names
:
859 # using PowerDecoder2, first, find the decoder index.
860 # (mapping name RA RB RC RS to in1, in2, in3)
861 regnum
, is_vec
= yield from get_pdecode_idx_in(self
.dec2
, name
)
863 regnum
, is_vec
= yield from get_pdecode_idx_out(self
.dec2
, name
)
864 #regnum = yield getattr(self.decoder, name)
866 self
.namespace
[regname
] = regnum
867 print('reading reg %s %d' % (name
, regnum
), is_vec
)
868 reg_val
= self
.gpr(regnum
)
869 inputs
.append(reg_val
)
871 # "special" registers
872 for special
in info
.special_regs
:
873 if special
in special_sprs
:
874 inputs
.append(self
.spr
[special
])
876 inputs
.append(self
.namespace
[special
])
878 # clear trap (trap) NIA
882 results
= info
.func(self
, *inputs
)
885 # "inject" decorator takes namespace from function locals: we need to
886 # overwrite NIA being overwritten (sigh)
887 if self
.trap_nia
is not None:
888 self
.namespace
['NIA'] = self
.trap_nia
890 print("after func", self
.namespace
['CIA'], self
.namespace
['NIA'])
892 # detect if CA/CA32 already in outputs (sra*, basically)
895 output_names
= create_args(info
.write_regs
)
896 for name
in output_names
:
902 print("carry already done?", bin(already_done
))
903 if hasattr(self
.dec2
.e
.do
, "output_carry"):
904 carry_en
= yield self
.dec2
.e
.do
.output_carry
908 yield from self
.handle_carry_(inputs
, results
, already_done
)
910 # detect if overflow was in return result
913 for name
, output
in zip(output_names
, results
):
914 if name
== 'overflow':
917 if hasattr(self
.dec2
.e
.do
, "oe"):
918 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
919 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
923 print("internal overflow", overflow
, ov_en
, ov_ok
)
925 yield from self
.handle_overflow(inputs
, results
, overflow
)
927 if hasattr(self
.dec2
.e
.do
, "rc"):
928 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
932 self
.handle_comparison(results
)
934 # any modified return results?
936 for name
, output
in zip(output_names
, results
):
937 if name
== 'overflow': # ignore, done already (above)
939 if isinstance(output
, int):
940 output
= SelectableInt(output
, 256)
941 if name
in ['CA', 'CA32']:
943 print("writing %s to XER" % name
, output
)
944 self
.spr
['XER'][XER_bits
[name
]] = output
.value
946 print("NOT writing %s to XER" % name
, output
)
947 elif name
in info
.special_regs
:
948 print('writing special %s' % name
, output
, special_sprs
)
949 if name
in special_sprs
:
950 self
.spr
[name
] = output
952 self
.namespace
[name
].eq(output
)
954 print('msr written', hex(self
.msr
.value
))
956 regnum
= yield getattr(self
.decoder
, name
)
957 print('writing reg %d %s' % (regnum
, str(output
)))
959 output
= SelectableInt(output
.value
, 64)
960 self
.gpr
[regnum
] = output
962 print("end of call", self
.namespace
['CIA'], self
.namespace
['NIA'])
963 # UPDATE program counter
964 self
.pc
.update(self
.namespace
)
968 """Decorator factory.
970 this decorator will "inject" variables into the function's namespace,
971 from the *dictionary* in self.namespace. it therefore becomes possible
972 to make it look like a whole stack of variables which would otherwise
973 need "self." inserted in front of them (*and* for those variables to be
974 added to the instance) "appear" in the function.
976 "self.namespace['SI']" for example becomes accessible as just "SI" but
977 *only* inside the function, when decorated.
979 def variable_injector(func
):
981 def decorator(*args
, **kwargs
):
983 func_globals
= func
.__globals
__ # Python 2.6+
984 except AttributeError:
985 func_globals
= func
.func_globals
# Earlier versions.
987 context
= args
[0].namespace
# variables to be injected
988 saved_values
= func_globals
.copy() # Shallow copy of dict.
989 func_globals
.update(context
)
990 result
= func(*args
, **kwargs
)
991 print("globals after", func_globals
['CIA'], func_globals
['NIA'])
992 print("args[0]", args
[0].namespace
['CIA'],
993 args
[0].namespace
['NIA'])
994 args
[0].namespace
= func_globals
995 #exec (func.__code__, func_globals)
998 # func_globals = saved_values # Undo changes.
1004 return variable_injector