d8774b4c66d50c9dac2e0b36246196024340980a
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
16 from nmigen
.back
.pysim
import Settle
17 from functools
import wraps
19 from soc
.decoder
.orderedset
import OrderedSet
20 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
22 from soc
.decoder
.power_enums
import (spr_dict
, spr_byname
, XER_bits
,
24 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
25 from soc
.consts
import PIb
, MSRb
# big-endian (PowerISA versions)
27 from collections
import namedtuple
31 instruction_info
= namedtuple('instruction_info',
32 'func read_regs uninit_regs write_regs ' +
33 'special_regs op_fields form asmregs')
43 def swap_order(x
, nbytes
):
44 x
= x
.to_bytes(nbytes
, byteorder
='little')
45 x
= int.from_bytes(x
, byteorder
='big', signed
=False)
50 # TODO (lkcl): adjust other registers that should be in a particular order
51 # probably CA, CA32, and CR
68 def create_args(reglist
, extra
=None):
69 retval
= list(OrderedSet(reglist
))
70 retval
.sort(key
=lambda reg
: REG_SORT_ORDER
[reg
])
72 return [extra
] + retval
78 def __init__(self
, row_bytes
=8, initial_mem
=None):
80 self
.bytes_per_word
= row_bytes
81 self
.word_log2
= math
.ceil(math
.log2(row_bytes
))
82 print("Sim-Mem", initial_mem
, self
.bytes_per_word
, self
.word_log2
)
86 # different types of memory data structures recognised (for convenience)
87 if isinstance(initial_mem
, list):
88 initial_mem
= (0, initial_mem
)
89 if isinstance(initial_mem
, tuple):
90 startaddr
, mem
= initial_mem
92 for i
, val
in enumerate(mem
):
93 initial_mem
[startaddr
+ row_bytes
*i
] = (val
, row_bytes
)
95 for addr
, (val
, width
) in initial_mem
.items():
96 #val = swap_order(val, width)
97 self
.st(addr
, val
, width
, swap
=False)
99 def _get_shifter_mask(self
, wid
, remainder
):
100 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
102 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
104 shifter
= remainder
* 8
105 mask
= (1 << (wid
* 8)) - 1
106 print("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
109 # TODO: Implement ld/st of lesser width
110 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
111 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
112 remainder
= address
& (self
.bytes_per_word
- 1)
113 address
= address
>> self
.word_log2
114 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
115 if address
in self
.mem
:
116 val
= self
.mem
[address
]
121 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
123 if width
!= self
.bytes_per_word
:
124 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
125 print("masking", hex(val
), hex(mask
<< shifter
), shifter
)
126 val
= val
& (mask
<< shifter
)
129 val
= swap_order(val
, width
)
130 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
133 def st(self
, addr
, v
, width
=8, swap
=True):
135 remainder
= addr
& (self
.bytes_per_word
- 1)
136 addr
= addr
>> self
.word_log2
137 print("Writing 0x{:x} to ST 0x{:x} "
138 "memaddr 0x{:x}/{:x}".format(v
, staddr
, addr
, remainder
, swap
))
139 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
141 v
= swap_order(v
, width
)
142 if width
!= self
.bytes_per_word
:
147 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
148 val
&= ~
(mask
<< shifter
)
153 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
155 def __call__(self
, addr
, sz
):
156 val
= self
.ld(addr
.value
, sz
, swap
=False)
157 print("memread", addr
, sz
, val
)
158 return SelectableInt(val
, sz
*8)
160 def memassign(self
, addr
, sz
, val
):
161 print("memassign", addr
, sz
, val
)
162 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
166 def __init__(self
, decoder
, regfile
):
170 self
[i
] = SelectableInt(regfile
[i
], 64)
172 def __call__(self
, ridx
):
175 def set_form(self
, form
):
178 def getz(self
, rnum
):
179 # rnum = rnum.value # only SelectableInt allowed
180 print("GPR getzero", rnum
)
182 return SelectableInt(0, 64)
185 def _get_regnum(self
, attr
):
186 getform
= self
.sd
.sigforms
[self
.form
]
187 rnum
= getattr(getform
, attr
)
190 def ___getitem__(self
, attr
):
191 print("GPR getitem", attr
)
192 rnum
= self
._get
_regnum
(attr
)
193 return self
.regfile
[rnum
]
196 for i
in range(0, len(self
), 8):
199 s
.append("%08x" % self
[i
+j
].value
)
201 print("reg", "%2d" % i
, s
)
205 def __init__(self
, pc_init
=0):
206 self
.CIA
= SelectableInt(pc_init
, 64)
207 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
209 def update(self
, namespace
):
210 self
.CIA
= namespace
['NIA'].narrow(64)
211 self
.NIA
= self
.CIA
+ SelectableInt(4, 64)
212 namespace
['CIA'] = self
.CIA
213 namespace
['NIA'] = self
.NIA
216 # Simple-V: see https://libre-soc.org/openpower/sv
218 def __init__(self
, init
=0):
219 self
.spr
= SelectableInt(init
, 32)
220 # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
221 self
.maxvl
= FieldSelectableInt(self
.spr
, tuple(range(0,7)))
222 self
.vl
= FieldSelectableInt(self
.spr
, tuple(range(7,14)))
223 self
.srcstep
= FieldSelectableInt(self
.spr
, tuple(range(14,21)))
224 self
.dststep
= FieldSelectableInt(self
.spr
, tuple(range(21,28)))
225 self
.subvl
= FieldSelectableInt(self
.spr
, tuple(range(28,30)))
226 self
.svstep
= FieldSelectableInt(self
.spr
, tuple(range(30,32)))
231 def __init__(self
, init
=0):
232 self
.spr
= SelectableInt(init
, 24)
233 # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
234 self
.mmode
= FieldSelectableInt(self
.spr
, [0])
235 self
.mask
= FieldSelectableInt(self
.spr
, tuple(range(1,4)))
236 self
.elwidth
= FieldSelectableInt(self
.spr
, tuple(range(4,6)))
237 self
.ewsrc
= FieldSelectableInt(self
.spr
, tuple(range(6,8)))
238 self
.subvl
= FieldSelectableInt(self
.spr
, tuple(range(8,10)))
239 self
.extra
= FieldSelectableInt(self
.spr
, tuple(range(10,19)))
240 self
.mode
= FieldSelectableInt(self
.spr
, tuple(range(19,24)))
243 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
244 class SVP64PrefixFields
:
246 self
.insn
= SelectableInt(0, 32)
247 # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
248 self
.major
= FieldSelectableInt(self
.insn
, tuple(range(0,6)))
249 self
.pid
= FieldSelectableInt(self
.insn
, (7, 9)) # must be 0b11
250 rmfields
= [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
251 self
.rm
= FieldSelectableInt(self
.insn
, rmfields
)
255 def __init__(self
, dec2
, initial_sprs
={}):
258 for key
, v
in initial_sprs
.items():
259 if isinstance(key
, SelectableInt
):
261 key
= special_sprs
.get(key
, key
)
262 if isinstance(key
, int):
265 info
= spr_byname
[key
]
266 if not isinstance(v
, SelectableInt
):
267 v
= SelectableInt(v
, info
.length
)
270 def __getitem__(self
, key
):
271 print("get spr", key
)
272 print("dict", self
.items())
273 # if key in special_sprs get the special spr, otherwise return key
274 if isinstance(key
, SelectableInt
):
276 if isinstance(key
, int):
277 key
= spr_dict
[key
].SPR
278 key
= special_sprs
.get(key
, key
)
279 if key
== 'HSRR0': # HACK!
281 if key
== 'HSRR1': # HACK!
284 res
= dict.__getitem
__(self
, key
)
286 if isinstance(key
, int):
289 info
= spr_byname
[key
]
290 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
291 res
= dict.__getitem
__(self
, key
)
292 print("spr returning", key
, res
)
295 def __setitem__(self
, key
, value
):
296 if isinstance(key
, SelectableInt
):
298 if isinstance(key
, int):
299 key
= spr_dict
[key
].SPR
300 print("spr key", key
)
301 key
= special_sprs
.get(key
, key
)
302 if key
== 'HSRR0': # HACK!
303 self
.__setitem
__('SRR0', value
)
304 if key
== 'HSRR1': # HACK!
305 self
.__setitem
__('SRR1', value
)
306 print("setting spr", key
, value
)
307 dict.__setitem
__(self
, key
, value
)
309 def __call__(self
, ridx
):
314 # decoder2 - an instance of power_decoder2
315 # regfile - a list of initial values for the registers
316 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
317 # respect_pc - tracks the program counter. requires initial_insns
318 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
319 initial_mem
=None, initial_msr
=0,
321 initial_insns
=None, respect_pc
=False,
326 self
.bigendian
= bigendian
328 self
.is_svp64_mode
= False
329 self
.respect_pc
= respect_pc
330 if initial_sprs
is None:
332 if initial_mem
is None:
334 if initial_insns
is None:
336 assert self
.respect_pc
== False, "instructions required to honor pc"
338 print("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
339 print("ISACaller initial_msr", initial_msr
)
341 # "fake program counter" mode (for unit testing)
345 if isinstance(initial_mem
, tuple):
346 self
.fake_pc
= initial_mem
[0]
347 disasm_start
= self
.fake_pc
349 disasm_start
= initial_pc
351 # disassembly: we need this for now (not given from the decoder)
352 self
.disassembly
= {}
354 for i
, code
in enumerate(disassembly
):
355 self
.disassembly
[i
*4 + disasm_start
] = code
357 # set up registers, instruction memory, data memory, PC, SPRs, MSR
358 self
.gpr
= GPR(decoder2
, regfile
)
359 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
360 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
362 self
.svstate
= SVP64State(initial_svstate
)
363 self
.spr
= SPR(decoder2
, initial_sprs
)
364 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
367 # FPR (same as GPR except for FP nums)
368 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
369 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
370 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
371 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
373 # 2.3.2 LR (actually SPR #8) -- Done
374 # 2.3.3 CTR (actually SPR #9) -- Done
375 # 2.3.4 TAR (actually SPR #815)
376 # 3.2.2 p45 XER (actually SPR #1) -- Done
377 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
379 # create CR then allow portions of it to be "selectable" (below)
380 #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
381 self
.cr
= SelectableInt(initial_cr
, 64) # underlying reg
382 #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
384 # "undefined", just set to variable-bit-width int (use exts "max")
385 #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
388 self
.namespace
.update(self
.spr
)
389 self
.namespace
.update({'GPR': self
.gpr
,
392 'memassign': self
.memassign
,
397 'undefined': undefined
,
398 'mode_is_64bit': True,
402 # update pc to requested start point
403 self
.set_pc(initial_pc
)
405 # field-selectable versions of Condition Register TODO check bitranges?
408 bits
= tuple(range(i
*4+32, (i
+1)*4+32)) # errr... maybe?
409 _cr
= FieldSelectableInt(self
.cr
, bits
)
411 self
.namespace
["CR%d" % i
] = _cr
413 self
.decoder
= decoder2
.dec
416 def TRAP(self
, trap_addr
=0x700, trap_bit
=PIb
.TRAP
):
417 print("TRAP:", hex(trap_addr
), hex(self
.namespace
['MSR'].value
))
418 # store CIA(+4?) in SRR0, set NIA to 0x700
419 # store MSR in SRR1, set MSR to um errr something, have to check spec
420 self
.spr
['SRR0'].value
= self
.pc
.CIA
.value
421 self
.spr
['SRR1'].value
= self
.namespace
['MSR'].value
422 self
.trap_nia
= SelectableInt(trap_addr
, 64)
423 self
.spr
['SRR1'][trap_bit
] = 1 # change *copy* of MSR in SRR1
425 # set exception bits. TODO: this should, based on the address
426 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
427 # bits appropriately. however it turns out that *for now* in all
428 # cases (all trap_addrs) the exact same thing is needed.
429 self
.msr
[MSRb
.IR
] = 0
430 self
.msr
[MSRb
.DR
] = 0
431 self
.msr
[MSRb
.FE0
] = 0
432 self
.msr
[MSRb
.FE1
] = 0
433 self
.msr
[MSRb
.EE
] = 0
434 self
.msr
[MSRb
.RI
] = 0
435 self
.msr
[MSRb
.SF
] = 1
436 self
.msr
[MSRb
.TM
] = 0
437 self
.msr
[MSRb
.VEC
] = 0
438 self
.msr
[MSRb
.VSX
] = 0
439 self
.msr
[MSRb
.PR
] = 0
440 self
.msr
[MSRb
.FP
] = 0
441 self
.msr
[MSRb
.PMM
] = 0
442 self
.msr
[MSRb
.TEs
] = 0
443 self
.msr
[MSRb
.TEe
] = 0
444 self
.msr
[MSRb
.UND
] = 0
445 self
.msr
[MSRb
.LE
] = 1
447 def memassign(self
, ea
, sz
, val
):
448 self
.mem
.memassign(ea
, sz
, val
)
450 def prep_namespace(self
, formname
, op_fields
):
451 # TODO: get field names from form in decoder*1* (not decoder2)
452 # decoder2 is hand-created, and decoder1.sigform is auto-generated
454 # then "yield" fields only from op_fields rather than hard-coded
456 fields
= self
.decoder
.sigforms
[formname
]
457 for name
in op_fields
:
459 sig
= getattr(fields
, name
.upper())
461 sig
= getattr(fields
, name
)
463 # these are all opcode fields involved in index-selection of CR,
464 # and need to do "standard" arithmetic. CR[BA+32] for example
465 # would, if using SelectableInt, only be 5-bit.
466 if name
in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
467 self
.namespace
[name
] = val
469 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
471 self
.namespace
['XER'] = self
.spr
['XER']
472 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
473 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
475 def handle_carry_(self
, inputs
, outputs
, already_done
):
476 inv_a
= yield self
.dec2
.e
.do
.invert_in
478 inputs
[0] = ~inputs
[0]
480 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
482 imm
= yield self
.dec2
.e
.do
.imm_data
.data
483 inputs
.append(SelectableInt(imm
, 64))
484 assert len(outputs
) >= 1
485 print("outputs", repr(outputs
))
486 if isinstance(outputs
, list) or isinstance(outputs
, tuple):
492 print("gt input", x
, output
)
493 gt
= (gtu(x
, output
))
496 cy
= 1 if any(gts
) else 0
498 if not (1 & already_done
):
499 self
.spr
['XER'][XER_bits
['CA']] = cy
501 print("inputs", already_done
, inputs
)
503 # ARGH... different for OP_ADD... *sigh*...
504 op
= yield self
.dec2
.e
.do
.insn_type
505 if op
== MicrOp
.OP_ADD
.value
:
506 res32
= (output
.value
& (1 << 32)) != 0
507 a32
= (inputs
[0].value
& (1 << 32)) != 0
509 b32
= (inputs
[1].value
& (1 << 32)) != 0
512 cy32
= res32 ^ a32 ^ b32
513 print("CA32 ADD", cy32
)
517 print("input", x
, output
)
518 print(" x[32:64]", x
, x
[32:64])
519 print(" o[32:64]", output
, output
[32:64])
520 gt
= (gtu(x
[32:64], output
[32:64])) == SelectableInt(1, 1)
522 cy32
= 1 if any(gts
) else 0
523 print("CA32", cy32
, gts
)
524 if not (2 & already_done
):
525 self
.spr
['XER'][XER_bits
['CA32']] = cy32
527 def handle_overflow(self
, inputs
, outputs
, div_overflow
):
528 if hasattr(self
.dec2
.e
.do
, "invert_in"):
529 inv_a
= yield self
.dec2
.e
.do
.invert_in
531 inputs
[0] = ~inputs
[0]
533 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
535 imm
= yield self
.dec2
.e
.do
.imm_data
.data
536 inputs
.append(SelectableInt(imm
, 64))
537 assert len(outputs
) >= 1
538 print("handle_overflow", inputs
, outputs
, div_overflow
)
539 if len(inputs
) < 2 and div_overflow
is None:
542 # div overflow is different: it's returned by the pseudo-code
543 # because it's more complex than can be done by analysing the output
544 if div_overflow
is not None:
545 ov
, ov32
= div_overflow
, div_overflow
546 # arithmetic overflow can be done by analysing the input and output
547 elif len(inputs
) >= 2:
551 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
552 output_sgn
= exts(output
.value
, output
.bits
) < 0
553 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
554 output_sgn
!= input_sgn
[0] else 0
557 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
558 output32_sgn
= exts(output
.value
, 32) < 0
559 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
560 output32_sgn
!= input32_sgn
[0] else 0
562 self
.spr
['XER'][XER_bits
['OV']] = ov
563 self
.spr
['XER'][XER_bits
['OV32']] = ov32
564 so
= self
.spr
['XER'][XER_bits
['SO']]
566 self
.spr
['XER'][XER_bits
['SO']] = so
568 def handle_comparison(self
, outputs
):
570 assert isinstance(out
, SelectableInt
), \
571 "out zero not a SelectableInt %s" % repr(outputs
)
572 print("handle_comparison", out
.bits
, hex(out
.value
))
573 # TODO - XXX *processor* in 32-bit mode
574 # https://bugs.libre-soc.org/show_bug.cgi?id=424
576 # o32 = exts(out.value, 32)
577 # print ("handle_comparison exts 32 bit", hex(o32))
578 out
= exts(out
.value
, out
.bits
)
579 print("handle_comparison exts", hex(out
))
580 zero
= SelectableInt(out
== 0, 1)
581 positive
= SelectableInt(out
> 0, 1)
582 negative
= SelectableInt(out
< 0, 1)
583 SO
= self
.spr
['XER'][XER_bits
['SO']]
584 print("handle_comparison SO", SO
)
585 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
586 self
.crl
[0].eq(cr_field
)
588 def set_pc(self
, pc_val
):
589 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
590 self
.pc
.update(self
.namespace
)
593 """set up one instruction
596 pc
= self
.pc
.CIA
.value
600 ins
= self
.imem
.ld(pc
, 4, False, True)
602 raise KeyError("no instruction at 0x%x" % pc
)
603 print("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
604 print("CIA NIA", self
.respect_pc
, self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
606 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
607 yield self
.dec2
.dec
.bigendian
.eq(self
.bigendian
)
608 yield self
.dec2
.state
.msr
.eq(self
.msr
.value
)
609 yield self
.dec2
.state
.pc
.eq(pc
)
611 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
613 opcode
= yield self
.dec2
.dec
.opcode_in
614 pfx
= SVP64PrefixFields()
615 pfx
.insn
.value
= opcode
616 major
= pfx
.major
.asint(msb0
=True) # MSB0 inversion
617 print ("prefix test: opcode:", major
, bin(major
),
618 pfx
.insn
[7] == 0b1, pfx
.insn
[9] == 0b1)
619 self
.is_svp64_mode
= ((major
== 0b000001) and
620 pfx
.insn
[7].value
== 0b1 and
621 pfx
.insn
[9].value
== 0b1)
622 if not self
.is_svp64_mode
:
625 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
626 print ("svp64.rm", bin(pfx
.rm
.asint(msb0
=True)))
627 ins
= self
.imem
.ld(pc
+4, 4, False, True)
628 print(" svsetup: 0x%x 0x%x %s" % (pc
+4, ins
& 0xffffffff, bin(ins
)))
629 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
632 def execute_one(self
):
633 """execute one instruction
635 # get the disassembly code for this instruction
636 if self
.is_svp64_mode
:
637 code
= self
.disassembly
[self
._pc
+4]
638 print(" svp64 sim-execute", hex(self
._pc
), code
)
640 code
= self
.disassembly
[self
._pc
]
641 print("sim-execute", hex(self
._pc
), code
)
642 opname
= code
.split(' ')[0]
643 yield from self
.call(opname
)
645 if not self
.respect_pc
:
647 print("execute one, CIA NIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
649 def get_assembly_name(self
):
650 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
651 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
652 dec_insn
= yield self
.dec2
.e
.do
.insn
653 asmcode
= yield self
.dec2
.dec
.op
.asmcode
654 print("get assembly name asmcode", asmcode
, hex(dec_insn
))
655 asmop
= insns
.get(asmcode
, None)
656 int_op
= yield self
.dec2
.dec
.op
.internal_op
658 # sigh reconstruct the assembly instruction name
659 if hasattr(self
.dec2
.e
.do
, "oe"):
660 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
661 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
665 if hasattr(self
.dec2
.e
.do
, "rc"):
666 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
667 rc_ok
= yield self
.dec2
.e
.do
.rc
.ok
671 # grrrr have to special-case MUL op (see DecodeOE)
672 print("ov %d en %d rc %d en %d op %d" %
673 (ov_ok
, ov_en
, rc_ok
, rc_en
, int_op
))
674 if int_op
in [MicrOp
.OP_MUL_H64
.value
, MicrOp
.OP_MUL_H32
.value
]:
679 if not asmop
.endswith("."): # don't add "." to "andis."
682 if hasattr(self
.dec2
.e
.do
, "lk"):
683 lk
= yield self
.dec2
.e
.do
.lk
686 print("int_op", int_op
)
687 if int_op
in [MicrOp
.OP_B
.value
, MicrOp
.OP_BC
.value
]:
688 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
692 spr_msb
= yield from self
.get_spr_msb()
693 if int_op
== MicrOp
.OP_MFCR
.value
:
698 # XXX TODO: for whatever weird reason this doesn't work
699 # https://bugs.libre-soc.org/show_bug.cgi?id=390
700 if int_op
== MicrOp
.OP_MTCRF
.value
:
707 def get_spr_msb(self
):
708 dec_insn
= yield self
.dec2
.e
.do
.insn
709 return dec_insn
& (1 << 20) != 0 # sigh - XFF.spr[-1]?
711 def call(self
, name
):
712 name
= name
.strip() # remove spaces if not already done so
714 print("halted - not executing", name
)
717 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
718 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
719 asmop
= yield from self
.get_assembly_name()
720 print("call", name
, asmop
)
723 int_op
= yield self
.dec2
.dec
.op
.internal_op
724 spr_msb
= yield from self
.get_spr_msb()
726 instr_is_privileged
= False
727 if int_op
in [MicrOp
.OP_ATTN
.value
,
728 MicrOp
.OP_MFMSR
.value
,
729 MicrOp
.OP_MTMSR
.value
,
730 MicrOp
.OP_MTMSRD
.value
,
732 MicrOp
.OP_RFID
.value
]:
733 instr_is_privileged
= True
734 if int_op
in [MicrOp
.OP_MFSPR
.value
,
735 MicrOp
.OP_MTSPR
.value
] and spr_msb
:
736 instr_is_privileged
= True
738 print("is priv", instr_is_privileged
, hex(self
.msr
.value
),
740 # check MSR priv bit and whether op is privileged: if so, throw trap
741 if instr_is_privileged
and self
.msr
[MSRb
.PR
] == 1:
742 self
.TRAP(0x700, PIb
.PRIV
)
743 self
.namespace
['NIA'] = self
.trap_nia
744 self
.pc
.update(self
.namespace
)
747 # check halted condition
752 # check illegal instruction
754 if name
not in ['mtcrf', 'mtocrf']:
755 illegal
= name
!= asmop
758 print("illegal", name
, asmop
)
759 self
.TRAP(0x700, PIb
.ILLEG
)
760 self
.namespace
['NIA'] = self
.trap_nia
761 self
.pc
.update(self
.namespace
)
762 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
763 (name
, asmop
, self
.pc
.CIA
.value
))
766 info
= self
.instrs
[name
]
767 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
769 # preserve order of register names
770 input_names
= create_args(list(info
.read_regs
) +
771 list(info
.uninit_regs
))
774 # main registers (RT, RA ...)
776 for name
in input_names
:
777 regnum
= yield getattr(self
.decoder
, name
)
779 self
.namespace
[regname
] = regnum
780 print('reading reg %d' % regnum
)
781 inputs
.append(self
.gpr(regnum
))
783 # "special" registers
784 for special
in info
.special_regs
:
785 if special
in special_sprs
:
786 inputs
.append(self
.spr
[special
])
788 inputs
.append(self
.namespace
[special
])
790 # clear trap (trap) NIA
794 results
= info
.func(self
, *inputs
)
797 # "inject" decorator takes namespace from function locals: we need to
798 # overwrite NIA being overwritten (sigh)
799 if self
.trap_nia
is not None:
800 self
.namespace
['NIA'] = self
.trap_nia
802 print("after func", self
.namespace
['CIA'], self
.namespace
['NIA'])
804 # detect if CA/CA32 already in outputs (sra*, basically)
807 output_names
= create_args(info
.write_regs
)
808 for name
in output_names
:
814 print("carry already done?", bin(already_done
))
815 if hasattr(self
.dec2
.e
.do
, "output_carry"):
816 carry_en
= yield self
.dec2
.e
.do
.output_carry
820 yield from self
.handle_carry_(inputs
, results
, already_done
)
822 # detect if overflow was in return result
825 for name
, output
in zip(output_names
, results
):
826 if name
== 'overflow':
829 if hasattr(self
.dec2
.e
.do
, "oe"):
830 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
831 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
835 print("internal overflow", overflow
, ov_en
, ov_ok
)
837 yield from self
.handle_overflow(inputs
, results
, overflow
)
839 if hasattr(self
.dec2
.e
.do
, "rc"):
840 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
844 self
.handle_comparison(results
)
846 # any modified return results?
848 for name
, output
in zip(output_names
, results
):
849 if name
== 'overflow': # ignore, done already (above)
851 if isinstance(output
, int):
852 output
= SelectableInt(output
, 256)
853 if name
in ['CA', 'CA32']:
855 print("writing %s to XER" % name
, output
)
856 self
.spr
['XER'][XER_bits
[name
]] = output
.value
858 print("NOT writing %s to XER" % name
, output
)
859 elif name
in info
.special_regs
:
860 print('writing special %s' % name
, output
, special_sprs
)
861 if name
in special_sprs
:
862 self
.spr
[name
] = output
864 self
.namespace
[name
].eq(output
)
866 print('msr written', hex(self
.msr
.value
))
868 regnum
= yield getattr(self
.decoder
, name
)
869 print('writing reg %d %s' % (regnum
, str(output
)))
871 output
= SelectableInt(output
.value
, 64)
872 self
.gpr
[regnum
] = output
874 print("end of call", self
.namespace
['CIA'], self
.namespace
['NIA'])
875 # UPDATE program counter
876 self
.pc
.update(self
.namespace
)
880 """Decorator factory.
882 this decorator will "inject" variables into the function's namespace,
883 from the *dictionary* in self.namespace. it therefore becomes possible
884 to make it look like a whole stack of variables which would otherwise
885 need "self." inserted in front of them (*and* for those variables to be
886 added to the instance) "appear" in the function.
888 "self.namespace['SI']" for example becomes accessible as just "SI" but
889 *only* inside the function, when decorated.
891 def variable_injector(func
):
893 def decorator(*args
, **kwargs
):
895 func_globals
= func
.__globals
__ # Python 2.6+
896 except AttributeError:
897 func_globals
= func
.func_globals
# Earlier versions.
899 context
= args
[0].namespace
# variables to be injected
900 saved_values
= func_globals
.copy() # Shallow copy of dict.
901 func_globals
.update(context
)
902 result
= func(*args
, **kwargs
)
903 print("globals after", func_globals
['CIA'], func_globals
['NIA'])
904 print("args[0]", args
[0].namespace
['CIA'],
905 args
[0].namespace
['NIA'])
906 args
[0].namespace
= func_globals
907 #exec (func.__code__, func_globals)
910 # func_globals = saved_values # Undo changes.
916 return variable_injector