1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
16 from nmigen
.back
.pysim
import Settle
17 from functools
import wraps
19 from soc
.decoder
.orderedset
import OrderedSet
20 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
22 from soc
.decoder
.power_enums
import (spr_dict
, spr_byname
, XER_bits
,
23 insns
, MicrOp
, In1Sel
, In2Sel
, In3Sel
,
25 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
26 from soc
.consts
import PIb
, MSRb
# big-endian (PowerISA versions)
27 from soc
.decoder
.power_svp64
import SVP64RM
, decode_extra
29 from collections
import namedtuple
33 instruction_info
= namedtuple('instruction_info',
34 'func read_regs uninit_regs write_regs ' +
35 'special_regs op_fields form asmregs')
45 def swap_order(x
, nbytes
):
46 x
= x
.to_bytes(nbytes
, byteorder
='little')
47 x
= int.from_bytes(x
, byteorder
='big', signed
=False)
52 # TODO (lkcl): adjust other registers that should be in a particular order
53 # probably CA, CA32, and CR
70 def create_args(reglist
, extra
=None):
71 retval
= list(OrderedSet(reglist
))
72 retval
.sort(key
=lambda reg
: REG_SORT_ORDER
[reg
])
74 return [extra
] + retval
80 def __init__(self
, row_bytes
=8, initial_mem
=None):
82 self
.bytes_per_word
= row_bytes
83 self
.word_log2
= math
.ceil(math
.log2(row_bytes
))
84 print("Sim-Mem", initial_mem
, self
.bytes_per_word
, self
.word_log2
)
88 # different types of memory data structures recognised (for convenience)
89 if isinstance(initial_mem
, list):
90 initial_mem
= (0, initial_mem
)
91 if isinstance(initial_mem
, tuple):
92 startaddr
, mem
= initial_mem
94 for i
, val
in enumerate(mem
):
95 initial_mem
[startaddr
+ row_bytes
*i
] = (val
, row_bytes
)
97 for addr
, (val
, width
) in initial_mem
.items():
98 #val = swap_order(val, width)
99 self
.st(addr
, val
, width
, swap
=False)
101 def _get_shifter_mask(self
, wid
, remainder
):
102 shifter
= ((self
.bytes_per_word
- wid
) - remainder
) * \
104 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
106 shifter
= remainder
* 8
107 mask
= (1 << (wid
* 8)) - 1
108 print("width,rem,shift,mask", wid
, remainder
, hex(shifter
), hex(mask
))
111 # TODO: Implement ld/st of lesser width
112 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
113 print("ld from addr 0x{:x} width {:d}".format(address
, width
))
114 remainder
= address
& (self
.bytes_per_word
- 1)
115 address
= address
>> self
.word_log2
116 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
117 if address
in self
.mem
:
118 val
= self
.mem
[address
]
123 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address
, remainder
, val
))
125 if width
!= self
.bytes_per_word
:
126 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
127 print("masking", hex(val
), hex(mask
<< shifter
), shifter
)
128 val
= val
& (mask
<< shifter
)
131 val
= swap_order(val
, width
)
132 print("Read 0x{:x} from addr 0x{:x}".format(val
, address
))
135 def st(self
, addr
, v
, width
=8, swap
=True):
137 remainder
= addr
& (self
.bytes_per_word
- 1)
138 addr
= addr
>> self
.word_log2
139 print("Writing 0x{:x} to ST 0x{:x} "
140 "memaddr 0x{:x}/{:x}".format(v
, staddr
, addr
, remainder
, swap
))
141 assert remainder
& (width
- 1) == 0, "Unaligned access unsupported!"
143 v
= swap_order(v
, width
)
144 if width
!= self
.bytes_per_word
:
149 shifter
, mask
= self
._get
_shifter
_mask
(width
, remainder
)
150 val
&= ~
(mask
<< shifter
)
155 print("mem @ 0x{:x}: 0x{:x}".format(addr
, self
.mem
[addr
]))
157 def __call__(self
, addr
, sz
):
158 val
= self
.ld(addr
.value
, sz
, swap
=False)
159 print("memread", addr
, sz
, val
)
160 return SelectableInt(val
, sz
*8)
162 def memassign(self
, addr
, sz
, val
):
163 print("memassign", addr
, sz
, val
)
164 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
168 def __init__(self
, decoder
, isacaller
, svstate
, regfile
):
171 self
.isacaller
= isacaller
172 self
.svstate
= svstate
174 self
[i
] = SelectableInt(regfile
[i
], 64)
176 def __call__(self
, ridx
):
179 def set_form(self
, form
):
182 def getz(self
, rnum
):
183 # rnum = rnum.value # only SelectableInt allowed
184 print("GPR getzero", rnum
)
186 return SelectableInt(0, 64)
189 def _get_regnum(self
, attr
):
190 getform
= self
.sd
.sigforms
[self
.form
]
191 rnum
= getattr(getform
, attr
)
194 def ___getitem__(self
, attr
):
195 """ XXX currently not used
197 rnum
= self
._get
_regnum
(attr
)
198 offs
= self
.svstate
.srcstep
199 print("GPR getitem", attr
, rnum
, "srcoffs", offs
)
200 return self
.regfile
[rnum
]
203 for i
in range(0, len(self
), 8):
206 s
.append("%08x" % self
[i
+j
].value
)
208 print("reg", "%2d" % i
, s
)
212 def __init__(self
, pc_init
=0):
213 self
.CIA
= SelectableInt(pc_init
, 64)
214 self
.NIA
= self
.CIA
+ SelectableInt(4, 64) # only true for v3.0B!
216 def update_nia(self
, is_svp64
):
217 increment
= 8 if is_svp64
else 4
218 self
.NIA
= self
.CIA
+ SelectableInt(increment
, 64)
220 def update(self
, namespace
, is_svp64
):
221 """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
223 self
.CIA
= namespace
['NIA'].narrow(64)
224 self
.update_nia(is_svp64
)
225 namespace
['CIA'] = self
.CIA
226 namespace
['NIA'] = self
.NIA
229 # Simple-V: see https://libre-soc.org/openpower/sv
231 def __init__(self
, init
=0):
232 self
.spr
= SelectableInt(init
, 32)
233 # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
234 self
.maxvl
= FieldSelectableInt(self
.spr
, tuple(range(0,7)))
235 self
.vl
= FieldSelectableInt(self
.spr
, tuple(range(7,14)))
236 self
.srcstep
= FieldSelectableInt(self
.spr
, tuple(range(14,21)))
237 self
.dststep
= FieldSelectableInt(self
.spr
, tuple(range(21,28)))
238 self
.subvl
= FieldSelectableInt(self
.spr
, tuple(range(28,30)))
239 self
.svstep
= FieldSelectableInt(self
.spr
, tuple(range(30,32)))
244 def __init__(self
, init
=0):
245 self
.spr
= SelectableInt(init
, 24)
246 # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
247 self
.mmode
= FieldSelectableInt(self
.spr
, [0])
248 self
.mask
= FieldSelectableInt(self
.spr
, tuple(range(1,4)))
249 self
.elwidth
= FieldSelectableInt(self
.spr
, tuple(range(4,6)))
250 self
.ewsrc
= FieldSelectableInt(self
.spr
, tuple(range(6,8)))
251 self
.subvl
= FieldSelectableInt(self
.spr
, tuple(range(8,10)))
252 self
.extra
= FieldSelectableInt(self
.spr
, tuple(range(10,19)))
253 self
.mode
= FieldSelectableInt(self
.spr
, tuple(range(19,24)))
256 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
257 class SVP64PrefixFields
:
259 self
.insn
= SelectableInt(0, 32)
260 # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
261 self
.major
= FieldSelectableInt(self
.insn
, tuple(range(0,6)))
262 self
.pid
= FieldSelectableInt(self
.insn
, (7, 9)) # must be 0b11
263 rmfields
= [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
264 self
.rm
= FieldSelectableInt(self
.insn
, rmfields
)
267 SV64P_MAJOR_SIZE
= len(SVP64PrefixFields().major
.br
)
268 SV64P_PID_SIZE
= len(SVP64PrefixFields().pid
.br
)
269 SV64P_RM_SIZE
= len(SVP64PrefixFields().rm
.br
)
273 def __init__(self
, dec2
, initial_sprs
={}):
276 for key
, v
in initial_sprs
.items():
277 if isinstance(key
, SelectableInt
):
279 key
= special_sprs
.get(key
, key
)
280 if isinstance(key
, int):
283 info
= spr_byname
[key
]
284 if not isinstance(v
, SelectableInt
):
285 v
= SelectableInt(v
, info
.length
)
288 def __getitem__(self
, key
):
289 print("get spr", key
)
290 print("dict", self
.items())
291 # if key in special_sprs get the special spr, otherwise return key
292 if isinstance(key
, SelectableInt
):
294 if isinstance(key
, int):
295 key
= spr_dict
[key
].SPR
296 key
= special_sprs
.get(key
, key
)
297 if key
== 'HSRR0': # HACK!
299 if key
== 'HSRR1': # HACK!
302 res
= dict.__getitem
__(self
, key
)
304 if isinstance(key
, int):
307 info
= spr_byname
[key
]
308 dict.__setitem
__(self
, key
, SelectableInt(0, info
.length
))
309 res
= dict.__getitem
__(self
, key
)
310 print("spr returning", key
, res
)
313 def __setitem__(self
, key
, value
):
314 if isinstance(key
, SelectableInt
):
316 if isinstance(key
, int):
317 key
= spr_dict
[key
].SPR
318 print("spr key", key
)
319 key
= special_sprs
.get(key
, key
)
320 if key
== 'HSRR0': # HACK!
321 self
.__setitem
__('SRR0', value
)
322 if key
== 'HSRR1': # HACK!
323 self
.__setitem
__('SRR1', value
)
324 print("setting spr", key
, value
)
325 dict.__setitem
__(self
, key
, value
)
327 def __call__(self
, ridx
):
330 def get_pdecode_idx_in(dec2
, name
):
332 in1_sel
= yield op
.in1_sel
333 in2_sel
= yield op
.in2_sel
334 in3_sel
= yield op
.in3_sel
335 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
336 in1
= yield dec2
.e
.read_reg1
.data
337 in2
= yield dec2
.e
.read_reg2
.data
338 in3
= yield dec2
.e
.read_reg3
.data
339 in1_isvec
= yield dec2
.in1_isvec
340 in2_isvec
= yield dec2
.in2_isvec
341 in3_isvec
= yield dec2
.in3_isvec
342 print ("get_pdecode_idx", in1_sel
, In1Sel
.RA
.value
, in1
, in1_isvec
)
343 # identify which regnames map to in1/2/3
345 if (in1_sel
== In1Sel
.RA
.value
or
346 (in1_sel
== In1Sel
.RA_OR_ZERO
.value
and in1
!= 0)):
347 return in1
, in1_isvec
348 if in1_sel
== In1Sel
.RA_OR_ZERO
.value
:
349 return in1
, in1_isvec
351 if in2_sel
== In2Sel
.RB
.value
:
352 return in2
, in2_isvec
353 if in3_sel
== In3Sel
.RB
.value
:
354 return in3
, in3_isvec
355 # XXX TODO, RC doesn't exist yet!
357 assert False, "RC does not exist yet"
359 if in1_sel
== In1Sel
.RS
.value
:
360 return in1
, in1_isvec
361 if in2_sel
== In2Sel
.RS
.value
:
362 return in2
, in2_isvec
363 if in3_sel
== In3Sel
.RS
.value
:
364 return in3
, in3_isvec
368 def get_pdecode_cr_out(dec2
, name
):
370 out_sel
= yield op
.cr_out
371 out_bitfield
= yield dec2
.dec_cr_out
.cr_bitfield
.data
372 sv_cr_out
= yield op
.sv_cr_out
373 spec
= yield dec2
.crout_svdec
.spec
374 sv_override
= yield dec2
.dec_cr_out
.sv_override
375 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
376 out
= yield dec2
.e
.write_cr
.data
377 o_isvec
= yield dec2
.o_isvec
378 print ("get_pdecode_cr_out", out_sel
, CROutSel
.CR0
.value
, out
, o_isvec
)
379 print (" sv_cr_out", sv_cr_out
)
380 print (" cr_bf", out_bitfield
)
381 print (" spec", spec
)
382 print (" override", sv_override
)
383 # identify which regnames map to out / o2
385 if out_sel
== CROutSel
.CR0
.value
:
387 print ("get_pdecode_idx_out not found", name
)
391 def get_pdecode_idx_out(dec2
, name
):
393 out_sel
= yield op
.out_sel
394 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
395 out
= yield dec2
.e
.write_reg
.data
396 o_isvec
= yield dec2
.o_isvec
397 print ("get_pdecode_idx_out", out_sel
, OutSel
.RA
.value
, out
, o_isvec
)
398 # identify which regnames map to out / o2
400 if out_sel
== OutSel
.RA
.value
:
403 if out_sel
== OutSel
.RT
.value
:
405 print ("get_pdecode_idx_out not found", name
)
410 def get_pdecode_idx_out2(dec2
, name
):
412 print ("TODO: get_pdecode_idx_out2", name
)
417 # decoder2 - an instance of power_decoder2
418 # regfile - a list of initial values for the registers
419 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
420 # respect_pc - tracks the program counter. requires initial_insns
421 def __init__(self
, decoder2
, regfile
, initial_sprs
=None, initial_cr
=0,
422 initial_mem
=None, initial_msr
=0,
424 initial_insns
=None, respect_pc
=False,
429 self
.bigendian
= bigendian
431 self
.is_svp64_mode
= False
432 self
.respect_pc
= respect_pc
433 if initial_sprs
is None:
435 if initial_mem
is None:
437 if initial_insns
is None:
439 assert self
.respect_pc
== False, "instructions required to honor pc"
441 print("ISACaller insns", respect_pc
, initial_insns
, disassembly
)
442 print("ISACaller initial_msr", initial_msr
)
444 # "fake program counter" mode (for unit testing)
448 if isinstance(initial_mem
, tuple):
449 self
.fake_pc
= initial_mem
[0]
450 disasm_start
= self
.fake_pc
452 disasm_start
= initial_pc
454 # disassembly: we need this for now (not given from the decoder)
455 self
.disassembly
= {}
457 for i
, code
in enumerate(disassembly
):
458 self
.disassembly
[i
*4 + disasm_start
] = code
460 # set up registers, instruction memory, data memory, PC, SPRs, MSR
461 self
.svp64rm
= SVP64RM()
462 if isinstance(initial_svstate
, int):
463 initial_svstate
= SVP64State(initial_svstate
)
464 self
.svstate
= initial_svstate
465 self
.gpr
= GPR(decoder2
, self
, self
.svstate
, regfile
)
466 self
.mem
= Mem(row_bytes
=8, initial_mem
=initial_mem
)
467 self
.imem
= Mem(row_bytes
=4, initial_mem
=initial_insns
)
469 self
.spr
= SPR(decoder2
, initial_sprs
)
470 self
.msr
= SelectableInt(initial_msr
, 64) # underlying reg
473 # FPR (same as GPR except for FP nums)
474 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
475 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
476 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
477 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
479 # 2.3.2 LR (actually SPR #8) -- Done
480 # 2.3.3 CTR (actually SPR #9) -- Done
481 # 2.3.4 TAR (actually SPR #815)
482 # 3.2.2 p45 XER (actually SPR #1) -- Done
483 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
485 # create CR then allow portions of it to be "selectable" (below)
486 #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
487 self
.cr
= SelectableInt(initial_cr
, 64) # underlying reg
488 #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
490 # "undefined", just set to variable-bit-width int (use exts "max")
491 #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
494 self
.namespace
.update(self
.spr
)
495 self
.namespace
.update({'GPR': self
.gpr
,
498 'memassign': self
.memassign
,
503 'undefined': undefined
,
504 'mode_is_64bit': True,
508 # update pc to requested start point
509 self
.set_pc(initial_pc
)
511 # field-selectable versions of Condition Register TODO check bitranges?
514 bits
= tuple(range(i
*4+32, (i
+1)*4+32)) # errr... maybe?
515 _cr
= FieldSelectableInt(self
.cr
, bits
)
517 self
.namespace
["CR%d" % i
] = _cr
519 self
.decoder
= decoder2
.dec
522 def TRAP(self
, trap_addr
=0x700, trap_bit
=PIb
.TRAP
):
523 print("TRAP:", hex(trap_addr
), hex(self
.namespace
['MSR'].value
))
524 # store CIA(+4?) in SRR0, set NIA to 0x700
525 # store MSR in SRR1, set MSR to um errr something, have to check spec
526 self
.spr
['SRR0'].value
= self
.pc
.CIA
.value
527 self
.spr
['SRR1'].value
= self
.namespace
['MSR'].value
528 self
.trap_nia
= SelectableInt(trap_addr
, 64)
529 self
.spr
['SRR1'][trap_bit
] = 1 # change *copy* of MSR in SRR1
531 # set exception bits. TODO: this should, based on the address
532 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
533 # bits appropriately. however it turns out that *for now* in all
534 # cases (all trap_addrs) the exact same thing is needed.
535 self
.msr
[MSRb
.IR
] = 0
536 self
.msr
[MSRb
.DR
] = 0
537 self
.msr
[MSRb
.FE0
] = 0
538 self
.msr
[MSRb
.FE1
] = 0
539 self
.msr
[MSRb
.EE
] = 0
540 self
.msr
[MSRb
.RI
] = 0
541 self
.msr
[MSRb
.SF
] = 1
542 self
.msr
[MSRb
.TM
] = 0
543 self
.msr
[MSRb
.VEC
] = 0
544 self
.msr
[MSRb
.VSX
] = 0
545 self
.msr
[MSRb
.PR
] = 0
546 self
.msr
[MSRb
.FP
] = 0
547 self
.msr
[MSRb
.PMM
] = 0
548 self
.msr
[MSRb
.TEs
] = 0
549 self
.msr
[MSRb
.TEe
] = 0
550 self
.msr
[MSRb
.UND
] = 0
551 self
.msr
[MSRb
.LE
] = 1
553 def memassign(self
, ea
, sz
, val
):
554 self
.mem
.memassign(ea
, sz
, val
)
556 def prep_namespace(self
, formname
, op_fields
):
557 # TODO: get field names from form in decoder*1* (not decoder2)
558 # decoder2 is hand-created, and decoder1.sigform is auto-generated
560 # then "yield" fields only from op_fields rather than hard-coded
562 fields
= self
.decoder
.sigforms
[formname
]
563 for name
in op_fields
:
565 sig
= getattr(fields
, name
.upper())
567 sig
= getattr(fields
, name
)
569 # these are all opcode fields involved in index-selection of CR,
570 # and need to do "standard" arithmetic. CR[BA+32] for example
571 # would, if using SelectableInt, only be 5-bit.
572 if name
in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
573 self
.namespace
[name
] = val
575 self
.namespace
[name
] = SelectableInt(val
, sig
.width
)
577 self
.namespace
['XER'] = self
.spr
['XER']
578 self
.namespace
['CA'] = self
.spr
['XER'][XER_bits
['CA']].value
579 self
.namespace
['CA32'] = self
.spr
['XER'][XER_bits
['CA32']].value
581 def handle_carry_(self
, inputs
, outputs
, already_done
):
582 inv_a
= yield self
.dec2
.e
.do
.invert_in
584 inputs
[0] = ~inputs
[0]
586 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
588 imm
= yield self
.dec2
.e
.do
.imm_data
.data
589 inputs
.append(SelectableInt(imm
, 64))
590 assert len(outputs
) >= 1
591 print("outputs", repr(outputs
))
592 if isinstance(outputs
, list) or isinstance(outputs
, tuple):
598 print("gt input", x
, output
)
599 gt
= (gtu(x
, output
))
602 cy
= 1 if any(gts
) else 0
604 if not (1 & already_done
):
605 self
.spr
['XER'][XER_bits
['CA']] = cy
607 print("inputs", already_done
, inputs
)
609 # ARGH... different for OP_ADD... *sigh*...
610 op
= yield self
.dec2
.e
.do
.insn_type
611 if op
== MicrOp
.OP_ADD
.value
:
612 res32
= (output
.value
& (1 << 32)) != 0
613 a32
= (inputs
[0].value
& (1 << 32)) != 0
615 b32
= (inputs
[1].value
& (1 << 32)) != 0
618 cy32
= res32 ^ a32 ^ b32
619 print("CA32 ADD", cy32
)
623 print("input", x
, output
)
624 print(" x[32:64]", x
, x
[32:64])
625 print(" o[32:64]", output
, output
[32:64])
626 gt
= (gtu(x
[32:64], output
[32:64])) == SelectableInt(1, 1)
628 cy32
= 1 if any(gts
) else 0
629 print("CA32", cy32
, gts
)
630 if not (2 & already_done
):
631 self
.spr
['XER'][XER_bits
['CA32']] = cy32
633 def handle_overflow(self
, inputs
, outputs
, div_overflow
):
634 if hasattr(self
.dec2
.e
.do
, "invert_in"):
635 inv_a
= yield self
.dec2
.e
.do
.invert_in
637 inputs
[0] = ~inputs
[0]
639 imm_ok
= yield self
.dec2
.e
.do
.imm_data
.ok
641 imm
= yield self
.dec2
.e
.do
.imm_data
.data
642 inputs
.append(SelectableInt(imm
, 64))
643 assert len(outputs
) >= 1
644 print("handle_overflow", inputs
, outputs
, div_overflow
)
645 if len(inputs
) < 2 and div_overflow
is None:
648 # div overflow is different: it's returned by the pseudo-code
649 # because it's more complex than can be done by analysing the output
650 if div_overflow
is not None:
651 ov
, ov32
= div_overflow
, div_overflow
652 # arithmetic overflow can be done by analysing the input and output
653 elif len(inputs
) >= 2:
657 input_sgn
= [exts(x
.value
, x
.bits
) < 0 for x
in inputs
]
658 output_sgn
= exts(output
.value
, output
.bits
) < 0
659 ov
= 1 if input_sgn
[0] == input_sgn
[1] and \
660 output_sgn
!= input_sgn
[0] else 0
663 input32_sgn
= [exts(x
.value
, 32) < 0 for x
in inputs
]
664 output32_sgn
= exts(output
.value
, 32) < 0
665 ov32
= 1 if input32_sgn
[0] == input32_sgn
[1] and \
666 output32_sgn
!= input32_sgn
[0] else 0
668 self
.spr
['XER'][XER_bits
['OV']] = ov
669 self
.spr
['XER'][XER_bits
['OV32']] = ov32
670 so
= self
.spr
['XER'][XER_bits
['SO']]
672 self
.spr
['XER'][XER_bits
['SO']] = so
674 def handle_comparison(self
, outputs
, cr_idx
=0):
676 assert isinstance(out
, SelectableInt
), \
677 "out zero not a SelectableInt %s" % repr(outputs
)
678 print("handle_comparison", out
.bits
, hex(out
.value
))
679 # TODO - XXX *processor* in 32-bit mode
680 # https://bugs.libre-soc.org/show_bug.cgi?id=424
682 # o32 = exts(out.value, 32)
683 # print ("handle_comparison exts 32 bit", hex(o32))
684 out
= exts(out
.value
, out
.bits
)
685 print("handle_comparison exts", hex(out
))
686 zero
= SelectableInt(out
== 0, 1)
687 positive
= SelectableInt(out
> 0, 1)
688 negative
= SelectableInt(out
< 0, 1)
689 SO
= self
.spr
['XER'][XER_bits
['SO']]
690 print("handle_comparison SO", SO
)
691 cr_field
= selectconcat(negative
, positive
, zero
, SO
)
692 self
.crl
[cr_idx
].eq(cr_field
)
694 def set_pc(self
, pc_val
):
695 self
.namespace
['NIA'] = SelectableInt(pc_val
, 64)
696 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
699 """set up one instruction
702 pc
= self
.pc
.CIA
.value
706 ins
= self
.imem
.ld(pc
, 4, False, True)
708 raise KeyError("no instruction at 0x%x" % pc
)
709 print("setup: 0x%x 0x%x %s" % (pc
, ins
& 0xffffffff, bin(ins
)))
710 print("CIA NIA", self
.respect_pc
, self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
712 yield self
.dec2
.sv_rm
.eq(0)
713 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff)
714 yield self
.dec2
.dec
.bigendian
.eq(self
.bigendian
)
715 yield self
.dec2
.state
.msr
.eq(self
.msr
.value
)
716 yield self
.dec2
.state
.pc
.eq(pc
)
717 yield self
.dec2
.state
.svstate
.eq(self
.svstate
.spr
.value
)
719 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
721 opcode
= yield self
.dec2
.dec
.opcode_in
722 pfx
= SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
723 pfx
.insn
.value
= opcode
724 major
= pfx
.major
.asint(msb0
=True) # MSB0 inversion
725 print ("prefix test: opcode:", major
, bin(major
),
726 pfx
.insn
[7] == 0b1, pfx
.insn
[9] == 0b1)
727 self
.is_svp64_mode
= ((major
== 0b000001) and
728 pfx
.insn
[7].value
== 0b1 and
729 pfx
.insn
[9].value
== 0b1)
730 self
.pc
.update_nia(self
.is_svp64_mode
)
731 if not self
.is_svp64_mode
:
734 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
735 print ("svp64.rm", bin(pfx
.rm
.asint(msb0
=True)))
736 print (" svstate.vl", self
.svstate
.vl
.asint(msb0
=True))
737 print (" svstate.mvl", self
.svstate
.maxvl
.asint(msb0
=True))
738 sv_rm
= pfx
.rm
.asint(msb0
=True)
739 ins
= self
.imem
.ld(pc
+4, 4, False, True)
740 print(" svsetup: 0x%x 0x%x %s" % (pc
+4, ins
& 0xffffffff, bin(ins
)))
741 yield self
.dec2
.dec
.raw_opcode_in
.eq(ins
& 0xffffffff) # v3.0B suffix
742 yield self
.dec2
.sv_rm
.eq(sv_rm
) # svp64 prefix
745 def execute_one(self
):
746 """execute one instruction
748 # get the disassembly code for this instruction
749 if self
.is_svp64_mode
:
750 code
= self
.disassembly
[self
._pc
+4]
751 print(" svp64 sim-execute", hex(self
._pc
), code
)
753 code
= self
.disassembly
[self
._pc
]
754 print("sim-execute", hex(self
._pc
), code
)
755 opname
= code
.split(' ')[0]
756 yield from self
.call(opname
)
758 # don't use this except in special circumstances
759 if not self
.respect_pc
:
762 print("execute one, CIA NIA", self
.pc
.CIA
.value
, self
.pc
.NIA
.value
)
764 def get_assembly_name(self
):
765 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
766 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
767 dec_insn
= yield self
.dec2
.e
.do
.insn
768 asmcode
= yield self
.dec2
.dec
.op
.asmcode
769 print("get assembly name asmcode", asmcode
, hex(dec_insn
))
770 asmop
= insns
.get(asmcode
, None)
771 int_op
= yield self
.dec2
.dec
.op
.internal_op
773 # sigh reconstruct the assembly instruction name
774 if hasattr(self
.dec2
.e
.do
, "oe"):
775 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
776 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
780 if hasattr(self
.dec2
.e
.do
, "rc"):
781 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
782 rc_ok
= yield self
.dec2
.e
.do
.rc
.ok
786 # grrrr have to special-case MUL op (see DecodeOE)
787 print("ov %d en %d rc %d en %d op %d" %
788 (ov_ok
, ov_en
, rc_ok
, rc_en
, int_op
))
789 if int_op
in [MicrOp
.OP_MUL_H64
.value
, MicrOp
.OP_MUL_H32
.value
]:
794 if not asmop
.endswith("."): # don't add "." to "andis."
797 if hasattr(self
.dec2
.e
.do
, "lk"):
798 lk
= yield self
.dec2
.e
.do
.lk
801 print("int_op", int_op
)
802 if int_op
in [MicrOp
.OP_B
.value
, MicrOp
.OP_BC
.value
]:
803 AA
= yield self
.dec2
.dec
.fields
.FormI
.AA
[0:-1]
807 spr_msb
= yield from self
.get_spr_msb()
808 if int_op
== MicrOp
.OP_MFCR
.value
:
813 # XXX TODO: for whatever weird reason this doesn't work
814 # https://bugs.libre-soc.org/show_bug.cgi?id=390
815 if int_op
== MicrOp
.OP_MTCRF
.value
:
822 def get_spr_msb(self
):
823 dec_insn
= yield self
.dec2
.e
.do
.insn
824 return dec_insn
& (1 << 20) != 0 # sigh - XFF.spr[-1]?
826 def call(self
, name
):
827 """call(opcode) - the primary execution point for instructions
829 name
= name
.strip() # remove spaces if not already done so
831 print("halted - not executing", name
)
834 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
835 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
836 asmop
= yield from self
.get_assembly_name()
837 print("call", name
, asmop
)
840 int_op
= yield self
.dec2
.dec
.op
.internal_op
841 spr_msb
= yield from self
.get_spr_msb()
843 instr_is_privileged
= False
844 if int_op
in [MicrOp
.OP_ATTN
.value
,
845 MicrOp
.OP_MFMSR
.value
,
846 MicrOp
.OP_MTMSR
.value
,
847 MicrOp
.OP_MTMSRD
.value
,
849 MicrOp
.OP_RFID
.value
]:
850 instr_is_privileged
= True
851 if int_op
in [MicrOp
.OP_MFSPR
.value
,
852 MicrOp
.OP_MTSPR
.value
] and spr_msb
:
853 instr_is_privileged
= True
855 print("is priv", instr_is_privileged
, hex(self
.msr
.value
),
857 # check MSR priv bit and whether op is privileged: if so, throw trap
858 if instr_is_privileged
and self
.msr
[MSRb
.PR
] == 1:
859 self
.TRAP(0x700, PIb
.PRIV
)
860 self
.namespace
['NIA'] = self
.trap_nia
861 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
864 # check halted condition
869 # check illegal instruction
871 if name
not in ['mtcrf', 'mtocrf']:
872 illegal
= name
!= asmop
875 print("illegal", name
, asmop
)
876 self
.TRAP(0x700, PIb
.ILLEG
)
877 self
.namespace
['NIA'] = self
.trap_nia
878 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
879 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
880 (name
, asmop
, self
.pc
.CIA
.value
))
883 info
= self
.instrs
[name
]
884 yield from self
.prep_namespace(info
.form
, info
.op_fields
)
886 # preserve order of register names
887 input_names
= create_args(list(info
.read_regs
) +
888 list(info
.uninit_regs
))
891 # get SVP64 entry for the current instruction
892 sv_rm
= self
.svp64rm
.instrs
.get(name
)
893 if sv_rm
is not None:
894 dest_cr
, src_cr
, src_byname
, dest_byname
= decode_extra(sv_rm
)
896 dest_cr
, src_cr
, src_byname
, dest_byname
= False, False, {}, {}
897 print ("sv rm", sv_rm
, dest_cr
, src_cr
, src_byname
, dest_byname
)
899 # get SVSTATE srcstep. TODO: dststep (twin predication)
900 srcstep
= self
.svstate
.srcstep
.asint(msb0
=True)
901 vl
= self
.svstate
.vl
.asint(msb0
=True)
902 mvl
= self
.svstate
.maxvl
.asint(msb0
=True)
904 # VL=0 in SVP64 mode means "do nothing: skip instruction"
905 if self
.is_svp64_mode
and vl
== 0:
906 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
907 print("end of call", self
.namespace
['CIA'], self
.namespace
['NIA'])
910 # main input registers (RT, RA ...)
912 for name
in input_names
:
913 # using PowerDecoder2, first, find the decoder index.
914 # (mapping name RA RB RC RS to in1, in2, in3)
915 regnum
, is_vec
= yield from get_pdecode_idx_in(self
.dec2
, name
)
917 # doing this is not part of svp64, it's because output
918 # registers, to be modified, need to be in the namespace.
919 regnum
, is_vec
= yield from get_pdecode_idx_out(self
.dec2
, name
)
920 # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
921 # XXX already done by PowerDecoder2, now
923 # regnum += srcstep # TODO, elwidth overrides
925 # in case getting the register number is needed, _RA, _RB
927 self
.namespace
[regname
] = regnum
928 print('reading reg %s %d' % (name
, regnum
), is_vec
)
929 reg_val
= self
.gpr(regnum
)
930 inputs
.append(reg_val
)
932 # "special" registers
933 for special
in info
.special_regs
:
934 if special
in special_sprs
:
935 inputs
.append(self
.spr
[special
])
937 inputs
.append(self
.namespace
[special
])
939 # clear trap (trap) NIA
943 results
= info
.func(self
, *inputs
)
946 # "inject" decorator takes namespace from function locals: we need to
947 # overwrite NIA being overwritten (sigh)
948 if self
.trap_nia
is not None:
949 self
.namespace
['NIA'] = self
.trap_nia
951 print("after func", self
.namespace
['CIA'], self
.namespace
['NIA'])
953 # detect if CA/CA32 already in outputs (sra*, basically)
956 output_names
= create_args(info
.write_regs
)
957 for name
in output_names
:
963 print("carry already done?", bin(already_done
))
964 if hasattr(self
.dec2
.e
.do
, "output_carry"):
965 carry_en
= yield self
.dec2
.e
.do
.output_carry
969 yield from self
.handle_carry_(inputs
, results
, already_done
)
971 # detect if overflow was in return result
974 for name
, output
in zip(output_names
, results
):
975 if name
== 'overflow':
978 if hasattr(self
.dec2
.e
.do
, "oe"):
979 ov_en
= yield self
.dec2
.e
.do
.oe
.oe
980 ov_ok
= yield self
.dec2
.e
.do
.oe
.ok
984 print("internal overflow", overflow
, ov_en
, ov_ok
)
986 yield from self
.handle_overflow(inputs
, results
, overflow
)
988 if hasattr(self
.dec2
.e
.do
, "rc"):
989 rc_en
= yield self
.dec2
.e
.do
.rc
.rc
993 regnum
, is_vec
= yield from get_pdecode_cr_out(self
.dec2
, "CR0")
994 self
.handle_comparison(results
, regnum
)
996 # svp64 loop can end early if the dest is scalar
997 svp64_dest_vector
= False
999 # any modified return results?
1001 for name
, output
in zip(output_names
, results
):
1002 if name
== 'overflow': # ignore, done already (above)
1004 if isinstance(output
, int):
1005 output
= SelectableInt(output
, 256)
1006 if name
in ['CA', 'CA32']:
1008 print("writing %s to XER" % name
, output
)
1009 self
.spr
['XER'][XER_bits
[name
]] = output
.value
1011 print("NOT writing %s to XER" % name
, output
)
1012 elif name
in info
.special_regs
:
1013 print('writing special %s' % name
, output
, special_sprs
)
1014 if name
in special_sprs
:
1015 self
.spr
[name
] = output
1017 self
.namespace
[name
].eq(output
)
1019 print('msr written', hex(self
.msr
.value
))
1021 regnum
, is_vec
= yield from get_pdecode_idx_out(self
.dec2
,
1024 # temporary hack for not having 2nd output
1025 regnum
= yield getattr(self
.decoder
, name
)
1027 # here's where we go "vector".
1029 # XXX already done by PowerDecoder2
1030 # regnum += srcstep # TODO, elwidth overrides
1031 svp64_dest_vector
= True
1032 print('writing reg %d %s' % (regnum
, str(output
)), is_vec
)
1033 if output
.bits
> 64:
1034 output
= SelectableInt(output
.value
, 64)
1035 self
.gpr
[regnum
] = output
1037 # check if it is the SVSTATE.src/dest step that needs incrementing
1038 # this is our Sub-Program-Counter loop from 0 to VL-1
1039 if self
.is_svp64_mode
:
1040 # XXX twin predication TODO
1041 vl
= self
.svstate
.vl
.asint(msb0
=True)
1042 mvl
= self
.svstate
.maxvl
.asint(msb0
=True)
1043 srcstep
= self
.svstate
.srcstep
.asint(msb0
=True)
1044 print (" svstate.vl", vl
)
1045 print (" svstate.mvl", mvl
)
1046 print (" svstate.srcstep", srcstep
)
1047 # check if srcstep needs incrementing by one, stop PC advancing
1048 if svp64_dest_vector
and srcstep
!= vl
-1:
1049 self
.svstate
.srcstep
+= SelectableInt(1, 7)
1050 self
.pc
.NIA
.value
= self
.pc
.CIA
.value
1051 self
.namespace
['NIA'] = self
.pc
.NIA
1052 print("end of sub-pc call", self
.namespace
['CIA'],
1053 self
.namespace
['NIA'])
1054 return # DO NOT allow PC to update whilst Sub-PC loop running
1056 self
.svstate
.srcstep
[0:7] = 0
1057 print (" svstate.srcstep loop end (PC to update)")
1058 self
.pc
.update_nia(self
.is_svp64_mode
)
1059 self
.namespace
['NIA'] = self
.pc
.NIA
1061 # UPDATE program counter
1062 self
.pc
.update(self
.namespace
, self
.is_svp64_mode
)
1063 print("end of call", self
.namespace
['CIA'], self
.namespace
['NIA'])
1067 """Decorator factory.
1069 this decorator will "inject" variables into the function's namespace,
1070 from the *dictionary* in self.namespace. it therefore becomes possible
1071 to make it look like a whole stack of variables which would otherwise
1072 need "self." inserted in front of them (*and* for those variables to be
1073 added to the instance) "appear" in the function.
1075 "self.namespace['SI']" for example becomes accessible as just "SI" but
1076 *only* inside the function, when decorated.
1078 def variable_injector(func
):
1080 def decorator(*args
, **kwargs
):
1082 func_globals
= func
.__globals
__ # Python 2.6+
1083 except AttributeError:
1084 func_globals
= func
.func_globals
# Earlier versions.
1086 context
= args
[0].namespace
# variables to be injected
1087 saved_values
= func_globals
.copy() # Shallow copy of dict.
1088 func_globals
.update(context
)
1089 result
= func(*args
, **kwargs
)
1090 print("globals after", func_globals
['CIA'], func_globals
['NIA'])
1091 print("args[0]", args
[0].namespace
['CIA'],
1092 args
[0].namespace
['NIA'])
1093 args
[0].namespace
= func_globals
1094 #exec (func.__code__, func_globals)
1097 # func_globals = saved_values # Undo changes.
1103 return variable_injector