src/soc/decoder/isa/caller.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Copyright (C) 2020 Michael Nolan
   4 # Funded by NLnet http://nlnet.nl
   5 """core of the python-based POWER9 simulator
   6
   7 this is part of a cycle-accurate POWER9 simulator.  its primary purpose is
   8 not speed, it is for both learning and educational purposes, as well as
   9 a method of verifying the HDL.
  10
  11 related bugs:
  12
  13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
  14 """
  15
  16 from nmigen.back.pysim import Settle
  17 from functools import wraps
  18 from copy import copy
  19 from soc.decoder.orderedset import OrderedSet
  20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
  21                                         selectconcat)
  22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
  23                                      insns, MicrOp, In1Sel, In2Sel, In3Sel,
  24                                      OutSel, CROutSel)
  25
  26 from soc.decoder.power_enums import SPR as DEC_SPR
  27
  28 from soc.decoder.helpers import exts, gtu, ltu, undefined
  29 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
  30 from soc.decoder.power_svp64 import SVP64RM, decode_extra
  31
  32 from soc.decoder.isa.radixmmu import RADIX
  33
  34 from collections import namedtuple
  35 import math
  36 import sys
  37
  38 instruction_info = namedtuple('instruction_info',
  39                               'func read_regs uninit_regs write_regs ' +
  40                               'special_regs op_fields form asmregs')
  41
  42 special_sprs = {
  43     'LR': 8,
  44     'CTR': 9,
  45     'TAR': 815,
  46     'XER': 1,
  47     'VRSAVE': 256}
  48
  49
  50 def swap_order(x, nbytes):
  51     x = x.to_bytes(nbytes, byteorder='little')
  52     x = int.from_bytes(x, byteorder='big', signed=False)
  53     return x
  54
  55
  56 REG_SORT_ORDER = {
  57     # TODO (lkcl): adjust other registers that should be in a particular order
  58     # probably CA, CA32, and CR
  59     "RT": 0,
  60     "RA": 0,
  61     "RB": 0,
  62     "RS": 0,
  63     "CR": 0,
  64     "LR": 0,
  65     "CTR": 0,
  66     "TAR": 0,
  67     "CA": 0,
  68     "CA32": 0,
  69     "MSR": 0,
  70
  71     "overflow": 1,
  72 }
  73
  74
  75 def create_args(reglist, extra=None):
  76     retval = list(OrderedSet(reglist))
  77     retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
  78     if extra is not None:
  79         return [extra] + retval
  80     return retval
  81
  82
  83
  84 class Mem:
  85
  86     def __init__(self, row_bytes=8, initial_mem=None):
  87         self.mem = {}
  88         self.bytes_per_word = row_bytes
  89         self.word_log2 = math.ceil(math.log2(row_bytes))
  90         print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
  91         if not initial_mem:
  92             return
  93
  94         # different types of memory data structures recognised (for convenience)
  95         if isinstance(initial_mem, list):
  96             initial_mem = (0, initial_mem)
  97         if isinstance(initial_mem, tuple):
  98             startaddr, mem = initial_mem
  99             initial_mem = {}
 100             for i, val in enumerate(mem):
 101                 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
 102
 103         for addr, (val, width) in initial_mem.items():
 104             #val = swap_order(val, width)
 105             self.st(addr, val, width, swap=False)
 106
 107     def _get_shifter_mask(self, wid, remainder):
 108         shifter = ((self.bytes_per_word - wid) - remainder) * \
 109             8  # bits per byte
 110         # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
 111         # BE/LE mode?
 112         shifter = remainder * 8
 113         mask = (1 << (wid * 8)) - 1
 114         print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
 115         return shifter, mask
 116
 117     # TODO: Implement ld/st of lesser width
 118     def ld(self, address, width=8, swap=True, check_in_mem=False):
 119         print("ld from addr 0x{:x} width {:d}".format(address, width))
 120         remainder = address & (self.bytes_per_word - 1)
 121         address = address >> self.word_log2
 122         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 123         if address in self.mem:
 124             val = self.mem[address]
 125         elif check_in_mem:
 126             return None
 127         else:
 128             val = 0
 129         print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
 130
 131         if width != self.bytes_per_word:
 132             shifter, mask = self._get_shifter_mask(width, remainder)
 133             print("masking", hex(val), hex(mask << shifter), shifter)
 134             val = val & (mask << shifter)
 135             val >>= shifter
 136         if swap:
 137             val = swap_order(val, width)
 138         print("Read 0x{:x} from addr 0x{:x}".format(val, address))
 139         return val
 140
 141     def st(self, addr, v, width=8, swap=True):
 142         staddr = addr
 143         remainder = addr & (self.bytes_per_word - 1)
 144         addr = addr >> self.word_log2
 145         print("Writing 0x{:x} to ST 0x{:x} "
 146               "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
 147         assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
 148         if swap:
 149             v = swap_order(v, width)
 150         if width != self.bytes_per_word:
 151             if addr in self.mem:
 152                 val = self.mem[addr]
 153             else:
 154                 val = 0
 155             shifter, mask = self._get_shifter_mask(width, remainder)
 156             val &= ~(mask << shifter)
 157             val |= v << shifter
 158             self.mem[addr] = val
 159         else:
 160             self.mem[addr] = v
 161         print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
 162
 163     def __call__(self, addr, sz):
 164         val = self.ld(addr.value, sz, swap=False)
 165         print("memread", addr, sz, val)
 166         return SelectableInt(val, sz*8)
 167
 168     def memassign(self, addr, sz, val):
 169         print("memassign", addr, sz, val)
 170         self.st(addr.value, val.value, sz, swap=False)
 171
 172
 173 class GPR(dict):
 174     def __init__(self, decoder, isacaller, svstate, regfile):
 175         dict.__init__(self)
 176         self.sd = decoder
 177         self.isacaller = isacaller
 178         self.svstate = svstate
 179         for i in range(32):
 180             self[i] = SelectableInt(regfile[i], 64)
 181
 182     def __call__(self, ridx):
 183         return self[ridx]
 184
 185     def set_form(self, form):
 186         self.form = form
 187
 188     def getz(self, rnum):
 189         # rnum = rnum.value # only SelectableInt allowed
 190         print("GPR getzero", rnum)
 191         if rnum == 0:
 192             return SelectableInt(0, 64)
 193         return self[rnum]
 194
 195     def _get_regnum(self, attr):
 196         getform = self.sd.sigforms[self.form]
 197         rnum = getattr(getform, attr)
 198         return rnum
 199
 200     def ___getitem__(self, attr):
 201         """ XXX currently not used
 202         """
 203         rnum = self._get_regnum(attr)
 204         offs = self.svstate.srcstep
 205         print("GPR getitem", attr, rnum, "srcoffs", offs)
 206         return self.regfile[rnum]
 207
 208     def dump(self):
 209         for i in range(0, len(self), 8):
 210             s = []
 211             for j in range(8):
 212                 s.append("%08x" % self[i+j].value)
 213             s = ' '.join(s)
 214             print("reg", "%2d" % i, s)
 215
 216
 217 class PC:
 218     def __init__(self, pc_init=0):
 219         self.CIA = SelectableInt(pc_init, 64)
 220         self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
 221
 222     def update_nia(self, is_svp64):
 223         increment = 8 if is_svp64 else 4
 224         self.NIA = self.CIA + SelectableInt(increment, 64)
 225
 226     def update(self, namespace, is_svp64):
 227         """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
 228         """
 229         self.CIA = namespace['NIA'].narrow(64)
 230         self.update_nia(is_svp64)
 231         namespace['CIA'] = self.CIA
 232         namespace['NIA'] = self.NIA
 233
 234
 235 # Simple-V: see https://libre-soc.org/openpower/sv
 236 class SVP64State:
 237     def __init__(self, init=0):
 238         self.spr = SelectableInt(init, 32)
 239         # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
 240         self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
 241         self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
 242         self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
 243         self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
 244         self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
 245         self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
 246
 247
 248 # SVP64 ReMap field
 249 class SVP64RMFields:
 250     def __init__(self, init=0):
 251         self.spr = SelectableInt(init, 24)
 252         # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
 253         self.mmode = FieldSelectableInt(self.spr, [0])
 254         self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
 255         self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
 256         self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
 257         self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
 258         self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
 259         self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
 260         # these cover the same extra field, split into parts as EXTRA2
 261         self.extra2 = list(range(4))
 262         self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
 263         self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
 264         self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
 265         self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
 266         self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
 267         # and here as well, but EXTRA3
 268         self.extra3 = list(range(3))
 269         self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
 270         self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
 271         self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
 272
 273
 274 SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)
 275 SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)
 276 SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)
 277 SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)
 278 SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)
 279 SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)
 280 SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)
 281 SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)
 282 SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)
 283
 284
 285 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
 286 class SVP64PrefixFields:
 287     def __init__(self):
 288         self.insn = SelectableInt(0, 32)
 289         # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
 290         self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
 291         self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
 292         rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
 293         self.rm = FieldSelectableInt(self.insn, rmfields)
 294
 295
 296 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
 297 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
 298 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
 299
 300
 301 class SPR(dict):
 302     def __init__(self, dec2, initial_sprs={}):
 303         self.sd = dec2
 304         dict.__init__(self)
 305         for key, v in initial_sprs.items():
 306             if isinstance(key, SelectableInt):
 307                 key = key.value
 308             key = special_sprs.get(key, key)
 309             if isinstance(key, int):
 310                 info = spr_dict[key]
 311             else:
 312                 info = spr_byname[key]
 313             if not isinstance(v, SelectableInt):
 314                 v = SelectableInt(v, info.length)
 315             self[key] = v
 316
 317     def __getitem__(self, key):
 318         print("get spr", key)
 319         print("dict", self.items())
 320         # if key in special_sprs get the special spr, otherwise return key
 321         if isinstance(key, SelectableInt):
 322             key = key.value
 323         if isinstance(key, int):
 324             key = spr_dict[key].SPR
 325         key = special_sprs.get(key, key)
 326         if key == 'HSRR0':  # HACK!
 327             key = 'SRR0'
 328         if key == 'HSRR1':  # HACK!
 329             key = 'SRR1'
 330         if key in self:
 331             res = dict.__getitem__(self, key)
 332         else:
 333             if isinstance(key, int):
 334                 info = spr_dict[key]
 335             else:
 336                 info = spr_byname[key]
 337             dict.__setitem__(self, key, SelectableInt(0, info.length))
 338             res = dict.__getitem__(self, key)
 339         print("spr returning", key, res)
 340         return res
 341
 342     def __setitem__(self, key, value):
 343         if isinstance(key, SelectableInt):
 344             key = key.value
 345         if isinstance(key, int):
 346             key = spr_dict[key].SPR
 347             print("spr key", key)
 348         key = special_sprs.get(key, key)
 349         if key == 'HSRR0':  # HACK!
 350             self.__setitem__('SRR0', value)
 351         if key == 'HSRR1':  # HACK!
 352             self.__setitem__('SRR1', value)
 353         print("setting spr", key, value)
 354         dict.__setitem__(self, key, value)
 355
 356     def __call__(self, ridx):
 357         return self[ridx]
 358
 359 def get_pdecode_idx_in(dec2, name):
 360     op = dec2.dec.op
 361     in1_sel = yield op.in1_sel
 362     in2_sel = yield op.in2_sel
 363     in3_sel = yield op.in3_sel
 364     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 365     in1 = yield dec2.e.read_reg1.data
 366     in2 = yield dec2.e.read_reg2.data
 367     in3 = yield dec2.e.read_reg3.data
 368     in1_isvec = yield dec2.in1_isvec
 369     in2_isvec = yield dec2.in2_isvec
 370     in3_isvec = yield dec2.in3_isvec
 371     print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
 372     # identify which regnames map to in1/2/3
 373     if name == 'RA':
 374         if (in1_sel == In1Sel.RA.value or
 375             (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
 376             return in1, in1_isvec
 377         if in1_sel == In1Sel.RA_OR_ZERO.value:
 378             return in1, in1_isvec
 379     elif name == 'RB':
 380         if in2_sel == In2Sel.RB.value:
 381             return in2, in2_isvec
 382         if in3_sel == In3Sel.RB.value:
 383             return in3, in3_isvec
 384     # XXX TODO, RC doesn't exist yet!
 385     elif name == 'RC':
 386         assert False, "RC does not exist yet"
 387     elif name == 'RS':
 388         if in1_sel == In1Sel.RS.value:
 389             return in1, in1_isvec
 390         if in2_sel == In2Sel.RS.value:
 391             return in2, in2_isvec
 392         if in3_sel == In3Sel.RS.value:
 393             return in3, in3_isvec
 394     return None, False
 395
 396
 397 def get_pdecode_cr_out(dec2, name):
 398     op = dec2.dec.op
 399     out_sel = yield op.cr_out
 400     out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
 401     sv_cr_out = yield op.sv_cr_out
 402     spec = yield dec2.crout_svdec.spec
 403     sv_override = yield dec2.dec_cr_out.sv_override
 404     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 405     out = yield dec2.e.write_cr.data
 406     o_isvec = yield dec2.o_isvec
 407     print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
 408     print ("    sv_cr_out", sv_cr_out)
 409     print ("    cr_bf", out_bitfield)
 410     print ("    spec", spec)
 411     print ("    override", sv_override)
 412     # identify which regnames map to out / o2
 413     if name == 'CR0':
 414         if out_sel == CROutSel.CR0.value:
 415             return out, o_isvec
 416     print ("get_pdecode_idx_out not found", name)
 417     return None, False
 418
 419
 420 def get_pdecode_idx_out(dec2, name):
 421     op = dec2.dec.op
 422     out_sel = yield op.out_sel
 423     # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
 424     out = yield dec2.e.write_reg.data
 425     o_isvec = yield dec2.o_isvec
 426     print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
 427     # identify which regnames map to out / o2
 428     if name == 'RA':
 429         if out_sel == OutSel.RA.value:
 430             return out, o_isvec
 431     elif name == 'RT':
 432         if out_sel == OutSel.RT.value:
 433             return out, o_isvec
 434     print ("get_pdecode_idx_out not found", name)
 435     return None, False
 436
 437
 438 # XXX TODO
 439 def get_pdecode_idx_out2(dec2, name):
 440     op = dec2.dec.op
 441     print ("TODO: get_pdecode_idx_out2", name)
 442     return None, False
 443
 444
 445 class ISACaller:
 446     # decoder2 - an instance of power_decoder2
 447     # regfile - a list of initial values for the registers
 448     # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
 449     # respect_pc - tracks the program counter.  requires initial_insns
 450     def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
 451                  initial_mem=None, initial_msr=0,
 452                  initial_svstate=0,
 453                  initial_insns=None, respect_pc=False,
 454                  disassembly=None,
 455                  initial_pc=0,
 456                  bigendian=False,
 457                  mmu=False):
 458
 459         self.bigendian = bigendian
 460         self.halted = False
 461         self.is_svp64_mode = False
 462         self.respect_pc = respect_pc
 463         if initial_sprs is None:
 464             initial_sprs = {}
 465         if initial_mem is None:
 466             initial_mem = {}
 467         if initial_insns is None:
 468             initial_insns = {}
 469             assert self.respect_pc == False, "instructions required to honor pc"
 470
 471         print("ISACaller insns", respect_pc, initial_insns, disassembly)
 472         print("ISACaller initial_msr", initial_msr)
 473
 474         # "fake program counter" mode (for unit testing)
 475         self.fake_pc = 0
 476         disasm_start = 0
 477         if not respect_pc:
 478             if isinstance(initial_mem, tuple):
 479                 self.fake_pc = initial_mem[0]
 480                 disasm_start = self.fake_pc
 481         else:
 482             disasm_start = initial_pc
 483
 484         # disassembly: we need this for now (not given from the decoder)
 485         self.disassembly = {}
 486         if disassembly:
 487             for i, code in enumerate(disassembly):
 488                 self.disassembly[i*4 + disasm_start] = code
 489
 490         # set up registers, instruction memory, data memory, PC, SPRs, MSR
 491         self.svp64rm = SVP64RM()
 492         if isinstance(initial_svstate, int):
 493             initial_svstate = SVP64State(initial_svstate)
 494         self.svstate = initial_svstate
 495         self.gpr = GPR(decoder2, self, self.svstate, regfile)
 496         self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
 497         if mmu:
 498             self.mem = RADIX(self.mem, self)
 499         self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
 500         self.pc = PC()
 501         self.spr = SPR(decoder2, initial_sprs)
 502         self.msr = SelectableInt(initial_msr, 64)  # underlying reg
 503
 504         # TODO, needed here:
 505         # FPR (same as GPR except for FP nums)
 506         # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
 507         #            note that mffs, mcrfs, mtfsf "manage" this FPSCR
 508         # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
 509         #         note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
 510         #         -- Done
 511         # 2.3.2 LR   (actually SPR #8) -- Done
 512         # 2.3.3 CTR  (actually SPR #9) -- Done
 513         # 2.3.4 TAR  (actually SPR #815)
 514         # 3.2.2 p45 XER  (actually SPR #1) -- Done
 515         # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
 516
 517         # create CR then allow portions of it to be "selectable" (below)
 518         #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
 519         self.cr = SelectableInt(initial_cr, 64)  # underlying reg
 520         #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
 521
 522         # "undefined", just set to variable-bit-width int (use exts "max")
 523         #self.undefined = SelectableInt(0, 256)  # TODO, not hard-code 256!
 524
 525         self.namespace = {}
 526         self.namespace.update(self.spr)
 527         self.namespace.update({'GPR': self.gpr,
 528                                'MEM': self.mem,
 529                                'SPR': self.spr,
 530                                'memassign': self.memassign,
 531                                'NIA': self.pc.NIA,
 532                                'CIA': self.pc.CIA,
 533                                'CR': self.cr,
 534                                'MSR': self.msr,
 535                                'undefined': undefined,
 536                                'mode_is_64bit': True,
 537                                'SO': XER_bits['SO']
 538                                })
 539
 540         # update pc to requested start point
 541         self.set_pc(initial_pc)
 542
 543         # field-selectable versions of Condition Register TODO check bitranges?
 544         self.crl = []
 545         for i in range(8):
 546             bits = tuple(range(i*4+32, (i+1)*4+32))  # errr... maybe?
 547             _cr = FieldSelectableInt(self.cr, bits)
 548             self.crl.append(_cr)
 549             self.namespace["CR%d" % i] = _cr
 550
 551         self.decoder = decoder2.dec
 552         self.dec2 = decoder2
 553
 554     def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
 555         print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
 556         # store CIA(+4?) in SRR0, set NIA to 0x700
 557         # store MSR in SRR1, set MSR to um errr something, have to check spec
 558         self.spr['SRR0'].value = self.pc.CIA.value
 559         self.spr['SRR1'].value = self.namespace['MSR'].value
 560         self.trap_nia = SelectableInt(trap_addr, 64)
 561         self.spr['SRR1'][trap_bit] = 1  # change *copy* of MSR in SRR1
 562
 563         # set exception bits.  TODO: this should, based on the address
 564         # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
 565         # bits appropriately.  however it turns out that *for now* in all
 566         # cases (all trap_addrs) the exact same thing is needed.
 567         self.msr[MSRb.IR] = 0
 568         self.msr[MSRb.DR] = 0
 569         self.msr[MSRb.FE0] = 0
 570         self.msr[MSRb.FE1] = 0
 571         self.msr[MSRb.EE] = 0
 572         self.msr[MSRb.RI] = 0
 573         self.msr[MSRb.SF] = 1
 574         self.msr[MSRb.TM] = 0
 575         self.msr[MSRb.VEC] = 0
 576         self.msr[MSRb.VSX] = 0
 577         self.msr[MSRb.PR] = 0
 578         self.msr[MSRb.FP] = 0
 579         self.msr[MSRb.PMM] = 0
 580         self.msr[MSRb.TEs] = 0
 581         self.msr[MSRb.TEe] = 0
 582         self.msr[MSRb.UND] = 0
 583         self.msr[MSRb.LE] = 1
 584
 585     def memassign(self, ea, sz, val):
 586         self.mem.memassign(ea, sz, val)
 587
 588     def prep_namespace(self, formname, op_fields):
 589         # TODO: get field names from form in decoder*1* (not decoder2)
 590         # decoder2 is hand-created, and decoder1.sigform is auto-generated
 591         # from spec
 592         # then "yield" fields only from op_fields rather than hard-coded
 593         # list, here.
 594         fields = self.decoder.sigforms[formname]
 595         for name in op_fields:
 596             if name == 'spr':
 597                 sig = getattr(fields, name.upper())
 598             else:
 599                 sig = getattr(fields, name)
 600             val = yield sig
 601             # these are all opcode fields involved in index-selection of CR,
 602             # and need to do "standard" arithmetic.  CR[BA+32] for example
 603             # would, if using SelectableInt, only be 5-bit.
 604             if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
 605                 self.namespace[name] = val
 606             else:
 607                 self.namespace[name] = SelectableInt(val, sig.width)
 608
 609         self.namespace['XER'] = self.spr['XER']
 610         self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
 611         self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
 612
 613     def handle_carry_(self, inputs, outputs, already_done):
 614         inv_a = yield self.dec2.e.do.invert_in
 615         if inv_a:
 616             inputs[0] = ~inputs[0]
 617
 618         imm_ok = yield self.dec2.e.do.imm_data.ok
 619         if imm_ok:
 620             imm = yield self.dec2.e.do.imm_data.data
 621             inputs.append(SelectableInt(imm, 64))
 622         assert len(outputs) >= 1
 623         print("outputs", repr(outputs))
 624         if isinstance(outputs, list) or isinstance(outputs, tuple):
 625             output = outputs[0]
 626         else:
 627             output = outputs
 628         gts = []
 629         for x in inputs:
 630             print("gt input", x, output)
 631             gt = (gtu(x, output))
 632             gts.append(gt)
 633         print(gts)
 634         cy = 1 if any(gts) else 0
 635         print("CA", cy, gts)
 636         if not (1 & already_done):
 637             self.spr['XER'][XER_bits['CA']] = cy
 638
 639         print("inputs", already_done, inputs)
 640         # 32 bit carry
 641         # ARGH... different for OP_ADD... *sigh*...
 642         op = yield self.dec2.e.do.insn_type
 643         if op == MicrOp.OP_ADD.value:
 644             res32 = (output.value & (1 << 32)) != 0
 645             a32 = (inputs[0].value & (1 << 32)) != 0
 646             if len(inputs) >= 2:
 647                 b32 = (inputs[1].value & (1 << 32)) != 0
 648             else:
 649                 b32 = False
 650             cy32 = res32 ^ a32 ^ b32
 651             print("CA32 ADD", cy32)
 652         else:
 653             gts = []
 654             for x in inputs:
 655                 print("input", x, output)
 656                 print("     x[32:64]", x, x[32:64])
 657                 print("     o[32:64]", output, output[32:64])
 658                 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
 659                 gts.append(gt)
 660             cy32 = 1 if any(gts) else 0
 661             print("CA32", cy32, gts)
 662         if not (2 & already_done):
 663             self.spr['XER'][XER_bits['CA32']] = cy32
 664
 665     def handle_overflow(self, inputs, outputs, div_overflow):
 666         if hasattr(self.dec2.e.do, "invert_in"):
 667             inv_a = yield self.dec2.e.do.invert_in
 668             if inv_a:
 669                 inputs[0] = ~inputs[0]
 670
 671         imm_ok = yield self.dec2.e.do.imm_data.ok
 672         if imm_ok:
 673             imm = yield self.dec2.e.do.imm_data.data
 674             inputs.append(SelectableInt(imm, 64))
 675         assert len(outputs) >= 1
 676         print("handle_overflow", inputs, outputs, div_overflow)
 677         if len(inputs) < 2 and div_overflow is None:
 678             return
 679
 680         # div overflow is different: it's returned by the pseudo-code
 681         # because it's more complex than can be done by analysing the output
 682         if div_overflow is not None:
 683             ov, ov32 = div_overflow, div_overflow
 684         # arithmetic overflow can be done by analysing the input and output
 685         elif len(inputs) >= 2:
 686             output = outputs[0]
 687
 688             # OV (64-bit)
 689             input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
 690             output_sgn = exts(output.value, output.bits) < 0
 691             ov = 1 if input_sgn[0] == input_sgn[1] and \
 692                 output_sgn != input_sgn[0] else 0
 693
 694             # OV (32-bit)
 695             input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
 696             output32_sgn = exts(output.value, 32) < 0
 697             ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
 698                 output32_sgn != input32_sgn[0] else 0
 699
 700         self.spr['XER'][XER_bits['OV']] = ov
 701         self.spr['XER'][XER_bits['OV32']] = ov32
 702         so = self.spr['XER'][XER_bits['SO']]
 703         so = so | ov
 704         self.spr['XER'][XER_bits['SO']] = so
 705
 706     def handle_comparison(self, outputs, cr_idx=0):
 707         out = outputs[0]
 708         assert isinstance(out, SelectableInt), \
 709             "out zero not a SelectableInt %s" % repr(outputs)
 710         print("handle_comparison", out.bits, hex(out.value))
 711         # TODO - XXX *processor* in 32-bit mode
 712         # https://bugs.libre-soc.org/show_bug.cgi?id=424
 713         # if is_32bit:
 714         #    o32 = exts(out.value, 32)
 715         #    print ("handle_comparison exts 32 bit", hex(o32))
 716         out = exts(out.value, out.bits)
 717         print("handle_comparison exts", hex(out))
 718         zero = SelectableInt(out == 0, 1)
 719         positive = SelectableInt(out > 0, 1)
 720         negative = SelectableInt(out < 0, 1)
 721         SO = self.spr['XER'][XER_bits['SO']]
 722         print("handle_comparison SO", SO)
 723         cr_field = selectconcat(negative, positive, zero, SO)
 724         self.crl[cr_idx].eq(cr_field)
 725
 726     def set_pc(self, pc_val):
 727         self.namespace['NIA'] = SelectableInt(pc_val, 64)
 728         self.pc.update(self.namespace, self.is_svp64_mode)
 729
 730     def setup_one(self):
 731         """set up one instruction
 732         """
 733         if self.respect_pc:
 734             pc = self.pc.CIA.value
 735         else:
 736             pc = self.fake_pc
 737         self._pc = pc
 738         ins = self.imem.ld(pc, 4, False, True)
 739         if ins is None:
 740             raise KeyError("no instruction at 0x%x" % pc)
 741         print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
 742         print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
 743
 744         yield self.dec2.sv_rm.eq(0)
 745         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
 746         yield self.dec2.dec.bigendian.eq(self.bigendian)
 747         yield self.dec2.state.msr.eq(self.msr.value)
 748         yield self.dec2.state.pc.eq(pc)
 749         yield self.dec2.state.svstate.eq(self.svstate.spr.value)
 750
 751         # SVP64.  first, check if the opcode is EXT001, and SVP64 id bits set
 752         yield Settle()
 753         opcode = yield self.dec2.dec.opcode_in
 754         pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
 755         pfx.insn.value = opcode
 756         major = pfx.major.asint(msb0=True) # MSB0 inversion
 757         print ("prefix test: opcode:", major, bin(major),
 758                 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
 759         self.is_svp64_mode = ((major == 0b000001) and
 760                               pfx.insn[7].value == 0b1 and
 761                               pfx.insn[9].value == 0b1)
 762         self.pc.update_nia(self.is_svp64_mode)
 763         self.namespace['NIA'] = self.pc.NIA
 764         if not self.is_svp64_mode:
 765             return
 766
 767         # in SVP64 mode.  decode/print out svp64 prefix, get v3.0B instruction
 768         print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
 769         print ("    svstate.vl", self.svstate.vl.asint(msb0=True))
 770         print ("    svstate.mvl", self.svstate.maxvl.asint(msb0=True))
 771         sv_rm = pfx.rm.asint(msb0=True)
 772         ins = self.imem.ld(pc+4, 4, False, True)
 773         print("     svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
 774         yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
 775         yield self.dec2.sv_rm.eq(sv_rm)                        # svp64 prefix
 776         yield Settle()
 777
 778     def execute_one(self):
 779         """execute one instruction
 780         """
 781         # get the disassembly code for this instruction
 782         if self.is_svp64_mode:
 783             code = self.disassembly[self._pc+4]
 784             print("    svp64 sim-execute", hex(self._pc), code)
 785         else:
 786             code = self.disassembly[self._pc]
 787             print("sim-execute", hex(self._pc), code)
 788         opname = code.split(' ')[0]
 789         yield from self.call(opname)
 790
 791         # don't use this except in special circumstances
 792         if not self.respect_pc:
 793             self.fake_pc += 4
 794
 795         print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
 796
 797     def get_assembly_name(self):
 798         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 799         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 800         dec_insn = yield self.dec2.e.do.insn
 801         asmcode = yield self.dec2.dec.op.asmcode
 802         print("get assembly name asmcode", asmcode, hex(dec_insn))
 803         asmop = insns.get(asmcode, None)
 804         int_op = yield self.dec2.dec.op.internal_op
 805
 806         # sigh reconstruct the assembly instruction name
 807         if hasattr(self.dec2.e.do, "oe"):
 808             ov_en = yield self.dec2.e.do.oe.oe
 809             ov_ok = yield self.dec2.e.do.oe.ok
 810         else:
 811             ov_en = False
 812             ov_ok = False
 813         if hasattr(self.dec2.e.do, "rc"):
 814             rc_en = yield self.dec2.e.do.rc.rc
 815             rc_ok = yield self.dec2.e.do.rc.ok
 816         else:
 817             rc_en = False
 818             rc_ok = False
 819         # grrrr have to special-case MUL op (see DecodeOE)
 820         print("ov %d en %d rc %d en %d op %d" %
 821               (ov_ok, ov_en, rc_ok, rc_en, int_op))
 822         if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
 823             print("mul op")
 824             if rc_en & rc_ok:
 825                 asmop += "."
 826         else:
 827             if not asmop.endswith("."):  # don't add "." to "andis."
 828                 if rc_en & rc_ok:
 829                     asmop += "."
 830         if hasattr(self.dec2.e.do, "lk"):
 831             lk = yield self.dec2.e.do.lk
 832             if lk:
 833                 asmop += "l"
 834         print("int_op", int_op)
 835         if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
 836             AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
 837             print("AA", AA)
 838             if AA:
 839                 asmop += "a"
 840         spr_msb = yield from self.get_spr_msb()
 841         if int_op == MicrOp.OP_MFCR.value:
 842             if spr_msb:
 843                 asmop = 'mfocrf'
 844             else:
 845                 asmop = 'mfcr'
 846         # XXX TODO: for whatever weird reason this doesn't work
 847         # https://bugs.libre-soc.org/show_bug.cgi?id=390
 848         if int_op == MicrOp.OP_MTCRF.value:
 849             if spr_msb:
 850                 asmop = 'mtocrf'
 851             else:
 852                 asmop = 'mtcrf'
 853         return asmop
 854
 855     def get_spr_msb(self):
 856         dec_insn = yield self.dec2.e.do.insn
 857         return dec_insn & (1 << 20) != 0  # sigh - XFF.spr[-1]?
 858
 859     def call(self, name):
 860         """call(opcode) - the primary execution point for instructions
 861         """
 862         name = name.strip()  # remove spaces if not already done so
 863         if self.halted:
 864             print("halted - not executing", name)
 865             return
 866
 867         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
 868         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
 869         asmop = yield from self.get_assembly_name()
 870         print("call", name, asmop)
 871
 872         # check privileged
 873         int_op = yield self.dec2.dec.op.internal_op
 874         spr_msb = yield from self.get_spr_msb()
 875
 876         instr_is_privileged = False
 877         if int_op in [MicrOp.OP_ATTN.value,
 878                       MicrOp.OP_MFMSR.value,
 879                       MicrOp.OP_MTMSR.value,
 880                       MicrOp.OP_MTMSRD.value,
 881                       # TODO: OP_TLBIE
 882                       MicrOp.OP_RFID.value]:
 883             instr_is_privileged = True
 884         if int_op in [MicrOp.OP_MFSPR.value,
 885                       MicrOp.OP_MTSPR.value] and spr_msb:
 886             instr_is_privileged = True
 887
 888         print("is priv", instr_is_privileged, hex(self.msr.value),
 889               self.msr[MSRb.PR])
 890         # check MSR priv bit and whether op is privileged: if so, throw trap
 891         if instr_is_privileged and self.msr[MSRb.PR] == 1:
 892             self.TRAP(0x700, PIb.PRIV)
 893             self.namespace['NIA'] = self.trap_nia
 894             self.pc.update(self.namespace, self.is_svp64_mode)
 895             return
 896
 897         # check halted condition
 898         if name == 'attn':
 899             self.halted = True
 900             return
 901
 902         # check illegal instruction
 903         illegal = False
 904         if name not in ['mtcrf', 'mtocrf']:
 905             illegal = name != asmop
 906
 907         if illegal:
 908             print("illegal", name, asmop)
 909             self.TRAP(0x700, PIb.ILLEG)
 910             self.namespace['NIA'] = self.trap_nia
 911             self.pc.update(self.namespace, self.is_svp64_mode)
 912             print("name %s != %s - calling ILLEGAL trap, PC: %x" %
 913                   (name, asmop, self.pc.CIA.value))
 914             return
 915
 916         info = self.instrs[name]
 917         yield from self.prep_namespace(info.form, info.op_fields)
 918
 919         # preserve order of register names
 920         input_names = create_args(list(info.read_regs) +
 921                                   list(info.uninit_regs))
 922         print(input_names)
 923
 924         # get SVP64 entry for the current instruction
 925         sv_rm = self.svp64rm.instrs.get(name)
 926         if sv_rm is not None:
 927             dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
 928         else:
 929             dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
 930         print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
 931
 932         # get SVSTATE srcstep.  TODO: dststep (twin predication)
 933         srcstep = self.svstate.srcstep.asint(msb0=True)
 934         vl = self.svstate.vl.asint(msb0=True)
 935         mvl = self.svstate.maxvl.asint(msb0=True)
 936
 937         # VL=0 in SVP64 mode means "do nothing: skip instruction"
 938         if self.is_svp64_mode and vl == 0:
 939             self.pc.update(self.namespace, self.is_svp64_mode)
 940             print("end of call", self.namespace['CIA'], self.namespace['NIA'])
 941             return
 942
 943         # main input registers (RT, RA ...)
 944         inputs = []
 945         for name in input_names:
 946             # using PowerDecoder2, first, find the decoder index.
 947             # (mapping name RA RB RC RS to in1, in2, in3)
 948             regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
 949             if regnum is None:
 950                 # doing this is not part of svp64, it's because output
 951                 # registers, to be modified, need to be in the namespace.
 952                 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
 953             # here's where we go "vector".  TODO: zero-testing (RA_IS_ZERO)
 954             # XXX already done by PowerDecoder2, now
 955             #if is_vec:
 956             #   regnum += srcstep # TODO, elwidth overrides
 957
 958             # in case getting the register number is needed, _RA, _RB
 959             regname = "_" + name
 960             self.namespace[regname] = regnum
 961             print('reading reg %s %d' % (name, regnum), is_vec)
 962             reg_val = self.gpr(regnum)
 963             inputs.append(reg_val)
 964
 965         # "special" registers
 966         for special in info.special_regs:
 967             if special in special_sprs:
 968                 inputs.append(self.spr[special])
 969             else:
 970                 inputs.append(self.namespace[special])
 971
 972         # clear trap (trap) NIA
 973         self.trap_nia = None
 974
 975         print("inputs", inputs)
 976         results = info.func(self, *inputs)
 977         print("results", results)
 978
 979         # "inject" decorator takes namespace from function locals: we need to
 980         # overwrite NIA being overwritten (sigh)
 981         if self.trap_nia is not None:
 982             self.namespace['NIA'] = self.trap_nia
 983
 984         print("after func", self.namespace['CIA'], self.namespace['NIA'])
 985
 986         # detect if CA/CA32 already in outputs (sra*, basically)
 987         already_done = 0
 988         if info.write_regs:
 989             output_names = create_args(info.write_regs)
 990             for name in output_names:
 991                 if name == 'CA':
 992                     already_done |= 1
 993                 if name == 'CA32':
 994                     already_done |= 2
 995
 996         print("carry already done?", bin(already_done))
 997         if hasattr(self.dec2.e.do, "output_carry"):
 998             carry_en = yield self.dec2.e.do.output_carry
 999         else:
1000             carry_en = False
1001         if carry_en:
1002             yield from self.handle_carry_(inputs, results, already_done)
1003
1004         # detect if overflow was in return result
1005         overflow = None
1006         if info.write_regs:
1007             for name, output in zip(output_names, results):
1008                 if name == 'overflow':
1009                     overflow = output
1010
1011         if hasattr(self.dec2.e.do, "oe"):
1012             ov_en = yield self.dec2.e.do.oe.oe
1013             ov_ok = yield self.dec2.e.do.oe.ok
1014         else:
1015             ov_en = False
1016             ov_ok = False
1017         print("internal overflow", overflow, ov_en, ov_ok)
1018         if ov_en & ov_ok:
1019             yield from self.handle_overflow(inputs, results, overflow)
1020
1021         if hasattr(self.dec2.e.do, "rc"):
1022             rc_en = yield self.dec2.e.do.rc.rc
1023         else:
1024             rc_en = False
1025         if rc_en:
1026             regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
1027             self.handle_comparison(results, regnum)
1028
1029         # any modified return results?
1030         if info.write_regs:
1031             for name, output in zip(output_names, results):
1032                 if name == 'overflow':  # ignore, done already (above)
1033                     continue
1034                 if isinstance(output, int):
1035                     output = SelectableInt(output, 256)
1036                 if name in ['CA', 'CA32']:
1037                     if carry_en:
1038                         print("writing %s to XER" % name, output)
1039                         self.spr['XER'][XER_bits[name]] = output.value
1040                     else:
1041                         print("NOT writing %s to XER" % name, output)
1042                 elif name in info.special_regs:
1043                     print('writing special %s' % name, output, special_sprs)
1044                     if name in special_sprs:
1045                         self.spr[name] = output
1046                     else:
1047                         self.namespace[name].eq(output)
1048                     if name == 'MSR':
1049                         print('msr written', hex(self.msr.value))
1050                 else:
1051                     regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
1052                                                 name)
1053                     if regnum is None:
1054                         # temporary hack for not having 2nd output
1055                         regnum = yield getattr(self.decoder, name)
1056                         is_vec = False
1057                     print('writing reg %d %s' % (regnum, str(output)), is_vec)
1058                     if output.bits > 64:
1059                         output = SelectableInt(output.value, 64)
1060                     self.gpr[regnum] = output
1061
1062         # check if it is the SVSTATE.src/dest step that needs incrementing
1063         # this is our Sub-Program-Counter loop from 0 to VL-1
1064         if self.is_svp64_mode:
1065             # XXX twin predication TODO
1066             vl = self.svstate.vl.asint(msb0=True)
1067             mvl = self.svstate.maxvl.asint(msb0=True)
1068             srcstep = self.svstate.srcstep.asint(msb0=True)
1069             print ("    svstate.vl", vl)
1070             print ("    svstate.mvl", mvl)
1071             print ("    svstate.srcstep", srcstep)
1072             # check if srcstep needs incrementing by one, stop PC advancing
1073             # svp64 loop can end early if the dest is scalar
1074             svp64_dest_vector = not (yield self.dec2.no_out_vec)
1075             if svp64_dest_vector and srcstep != vl-1:
1076                 self.svstate.srcstep += SelectableInt(1, 7)
1077                 self.pc.NIA.value = self.pc.CIA.value
1078                 self.namespace['NIA'] = self.pc.NIA
1079                 print("end of sub-pc call", self.namespace['CIA'],
1080                                      self.namespace['NIA'])
1081                 return # DO NOT allow PC to update whilst Sub-PC loop running
1082             # reset to zero
1083             self.svstate.srcstep[0:7] = 0
1084             print ("    svstate.srcstep loop end (PC to update)")
1085             self.pc.update_nia(self.is_svp64_mode)
1086             self.namespace['NIA'] = self.pc.NIA
1087
1088         # UPDATE program counter
1089         self.pc.update(self.namespace, self.is_svp64_mode)
1090         print("end of call", self.namespace['CIA'], self.namespace['NIA'])
1091
1092
1093 def inject():
1094     """Decorator factory.
1095
1096     this decorator will "inject" variables into the function's namespace,
1097     from the *dictionary* in self.namespace.  it therefore becomes possible
1098     to make it look like a whole stack of variables which would otherwise
1099     need "self." inserted in front of them (*and* for those variables to be
1100     added to the instance) "appear" in the function.
1101
1102     "self.namespace['SI']" for example becomes accessible as just "SI" but
1103     *only* inside the function, when decorated.
1104     """
1105     def variable_injector(func):
1106         @wraps(func)
1107         def decorator(*args, **kwargs):
1108             try:
1109                 func_globals = func.__globals__  # Python 2.6+
1110             except AttributeError:
1111                 func_globals = func.func_globals  # Earlier versions.
1112
1113             context = args[0].namespace  # variables to be injected
1114             saved_values = func_globals.copy()  # Shallow copy of dict.
1115             func_globals.update(context)
1116             result = func(*args, **kwargs)
1117             print("globals after", func_globals['CIA'], func_globals['NIA'])
1118             print("args[0]", args[0].namespace['CIA'],
1119                   args[0].namespace['NIA'])
1120             args[0].namespace = func_globals
1121             #exec (func.__code__, func_globals)
1122
1123             # finally:
1124             #    func_globals = saved_values  # Undo changes.
1125
1126             return result
1127
1128         return decorator
1129
1130     return variable_injector
1131
1132